component
UCC27614DR
Public Made by Adomby adom
TI Global Sourcing Parts, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownUCC27614DR
TI · Global Sourcing Parts · SOIC-8
UCC27614DR from TI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Driver bias supply; the datasheet gives a recommended VDD range of 4.5 V to 26 V and bypassing with two ceramic capacitors, generally ≥1 µF and 0.1 µF, referenced to GND. |
| 2 | IN | input | Non-inverting PWM input; the input pins are rated for -10 V to 30 V per the absolute maximum ratings. |
| 3 | EN | input | Enable or disable control pin; if not used, connect to VDD. |
| 4 | GND | power_in | Device ground or reference for all voltages on the device. |
| 5 | GND | power_in | Device ground or reference; pin 5 is a second GND pin to be connected alongside pin 4. |
| 6 | OUT | output | Output of the driver; DC output voltage is limited to -0.3 V to VDD + 0.3 V, and 200-ns pulses to -2 V to VDD + 3 V. |
| 7 | OUT | output | Output of the driver; pin 7 is a second OUT pin to be connected alongside pin 6, with the same voltage limits. |
| 8 | VDD | power_in | Driver bias supply; second VDD pin to be connected alongside pin 1, with the same bypassing requirement referenced to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TI |
| Package | SOIC-8 |
| Category | Global Sourcing Parts |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD quiescent supply current | IVDDq | 305 | 500 | μA | VIN+/VIN = 3.3 V, VIN- = 0 V, EN=VDD, VDD = 3.4 V | 5 | |
| VDD static supply current | IVDD | 0.64 | 0.92 | mA | VIN+/VIN = 3.3 V, VIN- = 0 V, EN = VDD | 5 | |
| VDD static supply current | IVDD | 0.71 | 1 | mA | VIN+/VIN = 0 V, VIN- = 0 V, EN = VDD | 5 | |
| VDD disable current | IDIS | 0.75 | 1 | mA | VIN+/VIN = 0 V, VIN- = 3.3 V, EN = 0 V | 5 | |
| VDD UVLO rising threshold | VVDD_ON | 3.8 | 4.1 | 4.4 | V | 5 | |
| VDD UVLO falling threshold | VVDD_OFF | 3.5 | 3.8 | 4.1 | V | 5 | |
| Input signal high threshold, output high (IN, IN+) | VIN_H | 1.8 | 2 | 2.3 | V | Output high, IN- = LOW, EN=HIGH | 5 |
| Input signal low threshold, output low (IN, IN+) | VIN_L | 0.8 | 1 | 1.2 | V | Output low, IN- = LOW, EN=HIGH | 5 |
| Input signal high threshold, output low (IN-) | VIN-_H | 1.8 | 2 | 2.3 | V | Output low, IN+ = HIGH, EN = high | 5 |
| Input signal low threshold, output high (IN-) | VIN-_L | 0.8 | 1 | 1.2 | V | Output high, IN+ = HIGH, EN = high | 5 |
| Enable signal high threshold | VEN_H | 1.8 | 2 | 2.3 | V | Output high, IN+/IN = high, IN- =0 V | 5 |
| Enable signal low threshold | VEN_L | 0.8 | 1 | 1.2 | V | Output low, IN+/IN = high, IN- = 0 V | 5 |
| OUTH pullup resistance | ROH | 2.5 | 4.5 | Ω | IOUT = -50 mA | 5 | |
| OUTL pulldown resistance | ROL | 0.34 | 0.55 | Ω | IOUT = 50 mA | 5 | |
| Rise time | tR | 4.5 | 6 | ns | CLOAD = 1.8 nF, 20% to 80%, VIN = 0 V to 3.3 V | 6 | |
| Fall time | tF | 4 | 5.5 | ns | CLOAD = 1.8 nF, 90% to 10%, VIN = 0 V to 3.3 V | 6 | |
| Turnon propagation delay | tD1 | 17.5 | 27 | ns | CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C | 6 | |
| Turn-off propagation delay | tD2 | 17.5 | 27 | ns | CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C | 6 | |
| Enable propagation delay | tPD_EN | 17.5 | 27 | ns | CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, TJ = 125°C | 6 | |
| Disable propagation delay | tPD_DIS | 17.5 | 27 | ns | CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw = 500 kHz, 50% duty cycle, TJ = 125°C | 6 | |
| VDD UVLO ON delay | tVDD+_OUT | 3.2 | 6 | µs | VDD = 0 V to 4.5 V in 100 ns; measured from VDD = 4.5 V to 10% of OUT | 6 | |
| Minimum input pulse width that passes to the output | tPWmin | 9 | 15 | ns | CLOAD = 1.8 nF, VIN = 0 V to 3.3 V, Fsw = 500 kHz, Vo > 1.5 V | 6 | |
| Supply voltage | VDD | 4.5 | 12 | 26 | V | 4 | |
| Input voltage (IN, IN+, IN-, EN) | -10 | 26 | V | 4 | |||
| Output voltage (OUT) | 0 | V | Printed maximum is VDD | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Supply voltage | VDD | -0.3 | 30 | V | 4 | ||
| Output Voltage (DC) | VOUT | -0.3 | V | Printed maximum is VDD + 0.3 V | 4 | ||
| Output Voltage (200-ns Pulse) | VOUT | -2 | V | 200-ns pulse; printed maximum is VDD + 3 V | 4 | ||
| Input Voltage (IN, EN, IN+, IN-) | -10 | 30 | V | 4 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Lead temperature, soldering | 300 | °C | Soldering, 10 s | 4 | |||
| Lead temperature, reflow | 260 | °C | Reflow | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| VDD dynamic operating current | IVDDO | 4 | mA | fSW = 1000 kHz, EN = VDD, VIN+/VIN = 0 V to 3.3 V PWM, VIN- = 0 V | 5 | ||
| Peak output source current | ISRC | 10 | A | VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz | 5 | ||
| Peak output sink current | ISNK | -10 | A | VDD = 12 V, CVDD = 10 µF, CL = 0.1 µF, f = 1 kHz | 5 | ||
| VDD UVLO hysteresis | VVDD_HYS | 0.3 | V | 5 | |||
| Input signal hysteresis (IN, IN+) | VIN_HYS | 1 | V | 5 | |||
| INx pin pulldown resistance | RIN | 120 | kΩ | IN+/IN = 3.3 V | 5 | ||
| Input signal hysteresis (IN-) | VIN-_HYS | 1 | V | 5 | |||
| IN- pin pullup resistance | RIN- | 200 | kΩ | IN- = 0 V | 5 | ||
| Enable signal hysteresis | VEN_HYS | 1 | V | 5 | |||
| EN pin pullup resistance | REN | 200 | kΩ | EN = 0 V | 5 | ||
| VDD UVLO OFF delay | tVDD-_OUT | 7.5 | us | VDD = 4.5 V to 3.4 V in 100 ns; measured from VDD = 3.4 V to 90% of OUT | 6 | ||
| Junction-to-ambient thermal resistance (SOIC D package) | RθJA | 126.4 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (SOIC D package) | RθJC(top) | 67 | °C/W | 4 | |||
| Junction-to-board thermal resistance (SOIC D package) | RθJB | 69.9 | °C/W | 4 | |||
| Junction-to-top characterization parameter (SOIC D package) | ψJT | 19.2 | °C/W | 4 | |||
| Junction-to-board characterization parameter (SOIC D package) | ψJB | 69.1 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
UCC27614DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
ucc27614dr-etched.step/ucc27614dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ucc27614dr.step/ucc27614dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TI datasheet (39 pp, sha256
7a79f2c30f85b692, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).