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SP3071EEN-L

Public Unreviewed

by Ray

MaxLinear RS-485 / RS-422 ICs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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SP3071EEN-L

MaxLinear · RS-485 / RS-422 ICs · SOIC-8

SP3071EEN-L from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Positive supply input, +3.3 V ±0.3 V. Supply current ICC ≈ 0.8 mA typical (1.5 mA max) with no load.
2 R output Receiver output (RO). CMOS output driven from the differential receiver comparing inputs A and B. VOH ≥ VCC − 0.6 V at IO = −1 mA; VOL ≤ 0.4 V at IO = 1 mA. Failsafe HIGH when A/B are open, shorted, or terminated with no driver.
3 D input Driver input (DI). CMOS logic input that sets the differential state of the Y/Z driver outputs. VIH ≥ 2 V, VIL ≤ 0.8 V, 100 mV hysteresis; input current ±1 µA max.
4 GND power_in Device ground reference (0 V).
5 Y output Non-inverting differential driver output. Follows DI (Y HIGH when DI HIGH). Together with Z forms the RS-485/RS-422 differential pair; VOD ≥ 1.5 V into RL = 54 Ω. Withstands −7 V to +12 V bus common-mode; ±15 kV HBM/Air-Gap and ±8 kV Contact ESD-protected.
6 Z output Inverting differential driver output. Complement of Y; drives LOW when DI is HIGH. Rated for −8 V to +13 V driver output voltage range; short-circuit current limited to ±250 mA (typ).
7 B input Inverting differential receiver input. Paired with A; receiver threshold VTH between −200 mV and −50 mV. Receiver input resistance ≥ 96 kΩ (1/8-unit load) allowing up to 256 nodes. Tolerates −7 V to +12 V common-mode, ±15 kV ESD-protected.
8 A input Non-inverting differential receiver input. Paired with B; drives R HIGH when (A − B) > VTH. Failsafe HIGH when open, shorted, or bus is idle-terminated. ±15 kV ESD-protected.

Key specifications

Parameter Value
Manufacturer MaxLinear
Package SOIC-8
Category Interface
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • SP3071EEN-L
  • SP3074E
  • SP3077E
  • SP3072E
  • SP3075E
  • SP3078E
  • SP3070E
  • SP3073E
  • SP3076E

CAD (KiCad official)

  • Symbol: SP3071EEN-L
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
sp3071een-l.step 122 KB You want the bare part, or you mark your own boards.
sp3071een-l-etched.step 1.9 MB You want the part with SP3071EEN-L already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 487 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: MaxLinear datasheet (19 pp, sha256 36aba08af75de5c4, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF