BD8303MUV-E2 from ROHM, in a QFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RT	input	Oscillation frequency set terminal. An external resistor R_RT to GND programs the internal oscillator frequency (0.2 to 1.0 MHz operating range; 600 kHz typ at R_RT = 51 kΩ).
2	INV	input	Error amplifier inverting input terminal. Compared against the internal 1.0V reference; sets the DC/DC output regulation point through the external feedback divider.
3	FB	output	Error amplifier output terminal. Loop-compensation network is connected between FB and INV. Sources ~20 µA / sinks ~1.3 mA.
4	GND	power_in	Signal/analog ground terminal for the IC.
5	STB	input	ON/OFF (standby) control terminal. IC turns ON when STB ≥ 2.5V and OFF when open or 0V. Internal ~400 kΩ pull-down to GND.
6	BOOT2	power_in	Output-side (SW2/secondary) high-side gate driver bootstrap supply input. External bootstrap capacitor to SW2 supplies the floating high-side driver. Max 7V vs SW2, 20V vs GND.
7	HG2	output	Output-side (secondary) high-side external N-channel FET gate drive terminal. Referenced to SW2. On-resistance ~4Ω typ.
8	SW2	passive	Output-side (secondary) switching node / coil connecting terminal. Return reference for the BOOT2/HG2 high-side driver. Max 15V absolute.
9	LG2	output	Output-side (secondary) low-side external N-channel FET gate drive terminal, referenced to PGND. Max duty ~90%, min ~10%; ~4Ω on-resistance.
10	PGND	power_in	Driver part power-ground terminal. Return for the low-side gate drivers; connect to system ground with a low-impedance path.
11	LG1	output	Input-side (primary) low-side external N-channel FET gate drive terminal, referenced to PGND. ~4Ω on-resistance; ~100 ns dead-time vs HG1.
12	SW1	passive	Input-side (primary) switching node / coil connecting terminal. Return reference for the BOOT1/HG1 floating high-side driver. Max 15V absolute.
13	HG1	output	Input-side (primary) high-side external N-channel FET gate drive terminal, referenced to SW1. Max duty ~90%. ~4Ω on-resistance.
14	BOOT1	power_in	Input-side (primary) high-side gate driver bootstrap supply input. External bootstrap capacitor to SW1 develops floating rail for HG1. Max 7V vs SW1, 20V vs GND.
15	REG	power_out	5V internal regulator (VREG) output terminal. Supplies internal circuitry and BOOT rail; requires an external 1.0 µF decoupling capacitor. 4.7 to 5.5V, 5.1V typ. Absolute max 7V.
16	VCC	power_in	Main power input terminal. Operating range 2.7V to 14V; absolute maximum 15V. Supplies the internal 5V regulator and control circuitry.

Key specifications

Parameter	Value
Manufacturer	ROHM
Package	QFN-16-EP(3x3)
Category	PMIC
Pins	16

Ordering variants

Same part, different packaging or reel option.

BD8303MUV-E2

CAD (KiCad official)

Symbol: BD8303MUV-E2
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: QFN-16-EP(3x3) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: ROHM datasheet (27 pp, sha256 a09f7b160668292c, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF