component
AT32F407VGT7
Public Made by Adomby adom
ARTERY Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAT32F407VGT7
ARTERY · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)
AT32F407VGT7 from ARTERY, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5V-tolerant (FT) GPIO; default function PE2, alternates SPI4_SCK/I2S4_CK, XMC_A23 and TRACECK. |
| 2 | PE3 | bidirectional | 5V-tolerant (FT) GPIO; default function PE3, alternates XMC_A19 and TRACED0. |
| 3 | PE4 | bidirectional | 5V-tolerant (FT) GPIO; default function PE4, alternates SPI4_NSS/I2S4_WS, XMC_A20 and TRACED1. |
| 4 | PE5 | bidirectional | 5V-tolerant (FT) GPIO; default function PE5, alternates SPI4_MISO, XMC_A21, TRACED2, with remap TMR9_CH1. |
| 5 | PE6 | bidirectional | 5V-tolerant (FT) GPIO; default function PE6, alternates SPI4_MOSI/I2S4_SD, XMC_A22 and TRACED3, with remap TMR9_CH2. |
| 6 | VBAT | power_in | Backup supply 1.8-3.6 V that powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off. |
| 7 | PC13/TAMPER-RTC | bidirectional | Standard-level (TC) I/O powered through the power switch limited to 3 mA; as an output it is limited to medium drive, 30 pF maximum load and cannot source current such as an LED; alternate function TAMPER-RTC. |
| 8 | PC14/OSC32_IN | bidirectional | Standard-level (TC) I/O powered through the power switch limited to 3 mA with the same output restrictions; alternate function OSC32_IN for the 32.768 kHz crystal. |
| 9 | PC15/OSC32_OUT | bidirectional | Standard-level (TC) I/O powered through the power switch limited to 3 mA with the same output restrictions; alternate function OSC32_OUT for the 32.768 kHz crystal. |
| 10 | VSS_5 | power_in | Ground pin that must be connected to the external supply system within the allowed range. |
| 11 | VDD_5 | power_in | Digital supply pin for the I/O pins and internal regulator, specified at VDD = 2.6 to 3.6 V. |
| 12 | OSC_IN | input | HSE oscillator input for a 4-25 MHz crystal or resonator (or external clock input). |
| 13 | OSC_OUT | output | HSE oscillator output for a 4-25 MHz crystal or resonator. |
| 14 | NRST | bidirectional | Active-low reset pin with a non-disconnectable pull-up RPU of 30-50 kΩ; VIL max 0.8 V and VIH min 2 V. |
| 15 | PC0 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN10 and SDIO2_D0. |
| 16 | PC1 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN11, SDIO2_D1 and ETH_MDC. |
| 17 | PC2 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN12, SDIO2_D2, ETH_MII_TXD2, with remap UART8_TX and XMC_NWE. |
| 18 | PC3 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN13, SDIO2_D3, XMC_A0, ETH_MII_TX_CLK, with remap UART8_RX. |
| 19 | VSSA | power_in | Analog ground for the ADC and DAC, which must be connected to VSS. |
| 20 | VREF- | power_in | Negative reference voltage input for the ADC and DAC, referenced to VSSA where connected internally per package. |
| 21 | VREF+ | power_in | Positive reference voltage for the ADC and DAC, between 2.6 V and VDDA. |
| 22 | VDDA | power_in | Analog supply for the ADC and DAC specified at 2.6-3.6 V that must be the same as VDD (max 300 mV difference). |
| 23 | PA0/WKUP | bidirectional | Standard-level (TC) GPIO; default PA0, with WKUP wake-up input and ADC123_IN0 plus timer and USART alternates; remap UART4_TX. |
| 24 | PA1 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN1, USART2_RTS, ETH_MII_RX_CLK, TMR2_CH2 and TMR5_CH2, with remap UART4_RX. |
| 25 | PA2 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN2, USART2_TX, ETH_MDIO, TMR2_CH3, TMR5_CH3 and TMR9_CH1, with remap SDIO2_CK and XMC_D4. |
| 26 | PA3 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC123_IN3, USART2_RX, ETH_MII_COL, TMR2_CH4, TMR5_CH4 and TMR9_CH2, with remap I2S2_MCK, SDIO2_CMD and XMC_D5. |
| 27 | VSS_4 | power_in | Ground pin that must be connected to the external supply system within the allowed range. |
| 28 | VDD_4 | power_in | Digital supply pin for the I/O pins and internal regulator, specified at VDD = 2.6 to 3.6 V. |
| 29 | PA4 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates DAC_OUT1, ADC12_IN4, USART2_CK, SPI1_NSS/I2S1_WS and SDIO2_D4, with remap USART6_TX, SPI3_NSS/I2S3_WS, SDIO2_D0 and XMC_D6. |
| 30 | PA5 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates DAC_OUT2, ADC12_IN5, SPI1_SCK/I2S1_CK and SDIO2_D5, with remap USART6_RX, SDIO2_D1 and XMC_D7. |
| 31 | PA6 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC12_IN6, SPI1_MISO, SDIO2_D6, TMR3_CH1, TMR8_BKIN and TMR13_CH1, with remap I2S2_MCK, SDIO2_D2 and TMR1_BKIN. |
| 32 | PA7 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC12_IN7, SPI1_MOSI/I2S1_SD, SDIO2_D7, ETH_MII_RX_DV, TMR3_CH2, TMR8_CH1N and TMR14_CH1, with remap SDIO2_D3 and TMR1_CH1N. |
| 33 | PC4 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC12_IN14, SDIO2_CK, XMC_NE4 and ETH_MII_RXD0. |
| 34 | PC5 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC12_IN15, SDIO2_CMD and ETH_MII_RXD1, with remap XMC_NOE. |
| 35 | PB0 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC12_IN8, I2S1_MCK, ETH_MII_RXD2, TMR3_CH3 and TMR8_CH2N, with remap TMR1_CH2N. |
| 36 | PB1 | bidirectional | 5V-tolerant analog-capable (FTa) GPIO; when used as analog it must stay below VDD + 0.3 V; alternates ADC12_IN9, SPIM_SCK, ETH_MII_RXD3, TMR3_CH4 and TMR8_CH3N, with remap TMR1_CH3N. |
| 37 | PB2/BOOT1 | bidirectional | 5V-tolerant (FT) GPIO; default function PB2, also used as the BOOT1 boot-mode pin. |
| 38 | PE7 | bidirectional | 5V-tolerant (FT) GPIO; default function PE7, alternates UART7_RX and XMC_D4, with remap TMR1_ETR. |
| 39 | PE8 | bidirectional | 5V-tolerant (FT) GPIO; default function PE8, alternates UART7_TX and XMC_D5, with remap TMR1_CH1N. |
| 40 | PE9 | bidirectional | 5V-tolerant (FT) GPIO; default function PE9, alternate XMC_D6, with remap TMR1_CH1. |
| 41 | PE10 | bidirectional | 5V-tolerant (FT) GPIO; default function PE10, alternate XMC_D7, with remap TMR1_CH2N. |
| 42 | PE11 | bidirectional | 5V-tolerant (FT) GPIO; default function PE11, alternates XMC_D8, SPI4_SCK/I2S4_CK and TMR1_CH2 as listed in the table. |
| 43 | PE12 | bidirectional | 5V-tolerant (FT) GPIO; default function PE12, alternates XMC_D9, SPI4_NSS/I2S4_WS and TMR1_CH3N as listed in the table. |
| 44 | PE13 | bidirectional | 5V-tolerant (FT) GPIO; default function PE13, alternates XMC_D10, SPI4_MISO and TMR1_CH3 as listed in the table. |
| 45 | PE14 | bidirectional | 5V-tolerant (FT) GPIO; default function PE14, alternates XMC_D11, SPI4_MOSI/I2S4_SD and TMR1_CH4 as listed in the table. |
| 46 | PE15 | bidirectional | 5V-tolerant (FT) GPIO; default function PE15, alternates XMC_D12 and TMR1_BKIN as listed in the table. |
| 47 | PB10 | bidirectional | 5V-tolerant (FT) GPIO; default function PB10, alternates USART3_TX, I2C2_SCL and ETH_MII_RX_ER, with remap I2S3_MCK, SPIM_IO0 and TMR2_CH3. |
| 48 | PB11 | bidirectional | 5V-tolerant (FT) GPIO; default function PB11, alternates USART3_RX, I2C2_SDA, ETH_MII_TX_EN and ETH_RMII_TX_EN, with remap SPIM_IO1 and TMR2_CH4. |
| 49 | VSS_1 | power_in | Ground pin that must be connected to the external supply system within the allowed range. |
| 50 | VDD_1 | power_in | Digital supply pin for the I/O pins and internal regulator, specified at VDD = 2.6 to 3.6 V. |
| 51 | PB12 | bidirectional | 5V-tolerant (FT) GPIO; default function PB12, alternates USART3_CK, CAN2_RX, I2C2_SMBA, SPI2_NSS/I2S2_WS, ETH_MII_TXD0 and TMR1_BKIN, with remap XMC_D13. |
| 52 | PB13 | bidirectional | 5V-tolerant (FT) GPIO; default function PB13, alternates USART3_CTS, CAN2_TX, SPI2_SCK/I2S2_CK, ETH_MII_TXD1 and TMR1_CH1N. |
| 53 | PB14 | bidirectional | 5V-tolerant (FT) GPIO; default function PB14, alternates USART3_RTS, SPI2_MISO, I2S2ext_SD and TMR1_CH2N, with remap TMR12_CH1 and XMC_D0. |
| 54 | PB15 | bidirectional | 5V-tolerant (FT) GPIO; default function PB15, alternates SPI2_MOSI/I2S2_SD and TMR1_CH3N, with remap TMR12_CH2. |
| 55 | PD8 | bidirectional | 5V-tolerant (FT) GPIO; default function PD8, alternates XMC_D13, USART3_TX, ETH_MII_RX_DV and ETH_RMII_CRS_DV as listed in the table. |
| 56 | PD9 | bidirectional | 5V-tolerant (FT) GPIO; default function PD9, alternates XMC_D14, USART3_RX, ETH_MII_RXD0 and ETH_RMII_RXD0 as listed in the table. |
| 57 | PD10 | bidirectional | 5V-tolerant (FT) GPIO; default function PD10, alternates XMC_D15, USART3_CK, ETH_MII_RXD1 and ETH_RMII_RXD1 as listed in the table. |
| 58 | PD11 | bidirectional | 5V-tolerant (FT) GPIO; default function PD11, alternates XMC_A16, USART3_CTS and ETH_MII_RXD2 as listed in the table. |
| 59 | PD12 | bidirectional | 5V-tolerant (FT) GPIO; default function PD12, alternates XMC_A17, USART3_RTS, ETH_MII_RXD3 and TMR4_CH1 as listed in the table. |
| 60 | PD13 | bidirectional | 5V-tolerant (FT) GPIO; default function PD13, alternates XMC_A18 and TMR4_CH2 as listed in the table. |
| 61 | PD14 | bidirectional | 5V-tolerant (FT) GPIO; default function PD14, alternates XMC_D0 and TMR4_CH3 as listed in the table. |
| 62 | PD15 | bidirectional | 5V-tolerant (FT) GPIO; default function PD15, alternates XMC_D1 and TMR4_CH4 as listed in the table. |
| 63 | PC6 | bidirectional | 5V-tolerant (FT) GPIO; default function PC6, alternates USART6_TX, I2S2_MCK and SDIO1_D6, TMR8_CH1, with remap XMC_D1 and TMR3_CH1. |
| 64 | PC7 | bidirectional | 5V-tolerant (FT) GPIO; default function PC7, alternates USART6_RX, I2S3_MCK, SDIO1_D7 and TMR8_CH2, with remap TMR3_CH2. |
| 65 | PC8 | bidirectional | 5V-tolerant (FT) GPIO; default function PC8, alternates USART6_CK, I2S4_MCK, SDIO1_D0 and TMR8_CH3, with remap TMR3_CH3. |
| 66 | PC9 | bidirectional | 5V-tolerant (FT) GPIO; default function PC9, alternates I2C3_SDA, SDIO1_D1 and TMR8_CH4, with remap TMR3_CH4. |
| 67 | PA8 | bidirectional | 5V-tolerant (FT) GPIO; default function PA8, alternates CLKOUT, USART1_CK, I2C3_SCL, USB_SOF, SPIM_NSS and TMR1_CH1. |
| 68 | PA9 | bidirectional | 5V-tolerant (FT) GPIO; default function PA9, alternates USART1_TX, I2C3_SMBA and TMR1_CH2; this is the USART1 bootloader TX pin. |
| 69 | PA10 | bidirectional | 5V-tolerant (FT) GPIO; default function PA10, alternates USART1_RX and TMR1_CH3, with remap I2S4_MCK; this is the USART1 bootloader RX pin. |
| 70 | PA11 | bidirectional | Standard-level (TC) GPIO; default function is USB_DM with alternates USART1_CTS, CAN1_RX, SPIM_IO0 and TMR1_CH4. |
| 71 | PA12 | bidirectional | Standard-level (TC) GPIO; default function is USB_DP with alternates USART1_RTS, CAN1_TX, SPIM_IO1 and TMR1_ETR. |
| 72 | PA13 | bidirectional | 5V-tolerant (FT) GPIO; default function is the JTMS-SWDIO debug pin. |
| 73 | NC | unconnected | Pin marked 未连接 (not connected) in the datasheet pin table. |
| 74 | VSS_2 | power_in | Ground pin that must be connected to the external supply system within the allowed range. |
| 75 | VDD_2 | power_in | Digital supply pin for the I/O pins and internal regulator, specified at VDD = 2.6 to 3.6 V. |
| 76 | PA14 | bidirectional | 5V-tolerant (FT) GPIO; default function is the JTCK-SWCLK debug pin. |
| 77 | PA15 | bidirectional | 5V-tolerant (FT) GPIO; default function is the JTDI debug pin, with alternates SPI3_NSS/I2S3_WS and remap PA15, SPI1_NSS/I2S1_WS, TMR2_CH1 and TMR2_ETR. |
| 78 | PC10 | bidirectional | 5V-tolerant (FT) GPIO; default function PC10, alternates UART4_TX and SDIO1_D2, with remap USART3_TX, SPI3_SCK and I2S3_CK. |
| 79 | PC11 | bidirectional | 5V-tolerant (FT) GPIO; default function PC11, alternates UART4_RX and SDIO1_D3, with remap USART3_RX, SPI3_MISO, I2S3ext_SD and XMC_D2. |
| 80 | PC12 | bidirectional | 5V-tolerant (FT) GPIO; default function PC12, alternates UART5_TX and SDIO1_CK, with remap USART3_CK, SPI3_MOSI, I2S3_SD and XMC_D3. |
| 81 | PD0 | bidirectional | 5V-tolerant (FT) GPIO; default function PD0, alternates XMC_D2 and CAN1_RX. |
| 82 | PD1 | bidirectional | 5V-tolerant (FT) GPIO; default function PD1, alternates XMC_D3 and CAN1_TX. |
| 83 | PD2 | bidirectional | 5V-tolerant (FT) GPIO; default function PD2, alternates UART5_RX, SDIO1_CMD and TMR3_ETR, with remap XMC_NWE. |
| 84 | PD3 | bidirectional | 5V-tolerant (FT) GPIO; default function PD3, alternates XMC_CLK and USART2_CTS. |
| 85 | PD4 | bidirectional | 5V-tolerant (FT) GPIO; default function PD4, alternates XMC_NOE and USART2_RTS. |
| 86 | PD5 | bidirectional | 5V-tolerant (FT) GPIO; default function PD5, alternates XMC_NWE and USART2_TX. |
| 87 | PD6 | bidirectional | 5V-tolerant (FT) GPIO; default function PD6, alternates XMC_NWAIT and USART2_RX. |
| 88 | PD7 | bidirectional | 5V-tolerant (FT) GPIO; default function PD7, alternates XMC_NE1/XMC_NCE2 and USART2_CK. |
| 89 | PB3 | bidirectional | 5V-tolerant (FT) GPIO; default function is the JTDO debug pin, with alternates SPI3_SCK/I2S3_CK and remap PB3, UART7_RX, SPI1_SCK, I2S1_CK, TRACESWO and TMR2_CH2. |
| 90 | PB4 | bidirectional | 5V-tolerant (FT) GPIO; default function is the NJTRST debug pin, with alternates SPI3_MISO/I2S3ext_SD and remap PB4, SPI1_MISO, I2C3_SDA, UART7_TX and TMR3_CH1. |
| 91 | PB5 | bidirectional | 5V-tolerant (FT) GPIO; default function PB5, alternates SPI3_MOSI/I2S3_SD, I2C1_SMBA and ETH_PPS_OUT, with remap SPI1_MOSI, I2S1_SD, CAN2_RX and TMR3_CH2. |
| 92 | PB6 | bidirectional | 5V-tolerant (FT) GPIO; default function PB6, alternates I2C1_SCL, SPIM_IO3 and TMR4_CH1, with remap USART1_TX, I2S1_MCK, SPI4_NSS/I2S4_WS and CAN2_TX. |
| 93 | PB7 | bidirectional | 5V-tolerant (FT) GPIO; default function PB7, alternates I2C1_SDA, XMC_NADV, SPIM_IO2 and TMR4_CH2, with remap USART1_RX, SPI4_SCK/I2S4_CK. |
| 94 | BOOT0 | input | Boot-mode select input; its weak pull-down (RPD 60-100 kΩ) cannot be disabled. |
| 95 | PB8 | bidirectional | 5V-tolerant (FT) GPIO; default function PB8, alternates SDIO1_D4, ETH_MII_TXD3, TMR4_CH3 and TMR10_CH1, with remap UART5_RX, SPI4_MISO, I2C1_SCL and CAN1_RX. |
| 96 | PB9 | bidirectional | 5V-tolerant (FT) GPIO; default function PB9, alternates SDIO1_D5, TMR4_CH4 and TMR11_CH1, with remap UART5_TX, SPI4_MOSI, I2S4_SD, I2C1_SDA and CAN1_TX. |
| 97 | PE0 | bidirectional | 5V-tolerant (FT) GPIO; default function PE0, alternates UART8_RX, XMC_NBL0 and TMR4_ETR as listed in the table. |
| 98 | PE1 | bidirectional | 5V-tolerant (FT) GPIO; default function PE1, alternates UART8_TX and XMC_NBL1 as listed in the table. |
| 99 | VSS_3 | power_in | Ground pin that must be connected to the external supply system within the allowed range. |
| 100 | VDD_3 | power_in | Digital supply pin for the I/O pins and internal regulator, specified at VDD = 2.6 to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ARTERY |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD and I/O pins | 2.6 | 3.6 | V | 1 | |||
| CPU maximum operating frequency | 240 | MHz | 1 | ||||
| External crystal oscillator frequency (HSE) | 4 | 25 | MHz | 1 | |||
| Factory-trimmed 48 MHz RC oscillator accuracy | -1 | 1 | % | 25 °C | 1 | ||
| Factory-trimmed 48 MHz RC oscillator accuracy | -2.5 | 2.5 | % | -40 °C to +105 °C | 1 | ||
| ADC conversion range | 0 | 3.6 | V | 1 | |||
| VBAT backup supply | VBAT | 1.8 | 3.6 | V | 37 | ||
| SD/MMC clock frequency in data transfer mode | fPP | 0 | 48 | MHz | CL ≤ 30 pF | 77 | |
| SD/MMC clock low time | tW(CKL) | 32 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC clock high time | tW(CKH) | 30 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC clock rise time | tr | 4 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC clock fall time | tf | 5 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC CMD and D input setup time to CK | tISU | 2 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC CMD and D input hold time from CK | tIH | 0 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC CMD and D output valid time (MMC and SD high-speed mode) | tOV | 6 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC CMD and D output hold time (MMC and SD high-speed mode) | tOH | 0 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC CMD and D output valid time (SD default mode) | tOVD | 7 | ns | CL ≤ 30 pF | 77 | ||
| SD/MMC CMD and D output hold time (SD default mode) | tOHD | 0.5 | ns | CL ≤ 30 pF | 77 | ||
| USB transceiver startup time (design-guaranteed) | tSTARTUP | 1 | μs | 78 | |||
| USB operating voltage VDD | VDD | 3 | 3.6 | V | 78 | ||
| USB differential input sensitivity | VDI | 0.2 | V | I (USB_DP，USB_DM) | 78 | ||
| USB differential common-mode range | VCM | 0.8 | 2.5 | V | 包含VDI范围 | 78 | |
| USB single-ended receiver threshold | VSE | 1.3 | 2 | V | 78 | ||
| USB static output low level | VOL | 0.3 | V | 1.24 kΩ的RL接至3.6 V | 78 | ||
| USB static output high level | VOH | 2.8 | 3.6 | V | 15 kΩ的RL接至VSS | 78 | |
| USB_DP internal pull-up resistance | RPU | 0.97 | 1.24 | 1.58 | kΩ | VIN = VSS | 78 |
| USB full-speed rise time | tr | 4 | 20 | ns | CL ≤ 50 pF | 78 | |
| USB full-speed fall time | tf | 4 | 20 | ns | CL ≤ 50 pF | 78 | |
| USB full-speed rise/fall time matching | trfm | 90 | 110 | % | 78 | ||
| USB full-speed output crossover voltage | VCRS | 1.3 | 2 | V | 78 | ||
| Ethernet operating voltage VDD | VDD | 3 | 3.6 | V | 79 | ||
| Ethernet MAC SMI MDC clock period | tMDC | 583 | 583.5 | 584 | ns | 1.71 MHz, fAHB = 72 MHz | 79 |
| Ethernet MAC SMI MDIO write data valid time | td(MDIO) | 13.5 | 14.5 | 15.5 | ns | 79 | |
| Ethernet MAC SMI MDIO read data setup time | tsu(MDIO) | 35 | ns | 79 | |||
| Ethernet MAC SMI MDIO read data hold time | th(MDIO) | 0 | ns | 79 |
CAD (KiCad official)
- Symbol:
AT32F407VGT7 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
at32f407vgt7-etched.step/at32f407vgt7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);at32f407vgt7.step/at32f407vgt7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ARTERY datasheet (94 pp, sha256
6b3438d4cf1137ac, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).