component
AK5554VN
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Asahi Kasei Microdevices Digital To Analog Converters (DACs), QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAK5554VN
Asahi Kasei Microdevices · Digital To Analog Converters (DACs) · QFN-48-EP(7x7)
AK5554VN from Asahi Kasei Microdevices, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal bonding; connect to AVSS. |
| 2 | VREFL1 | input | ADC low-level voltage reference input; normally connected to AVSS, and VREFL1-2 must be connected to AVSS. |
| 3 | VREFH1 | input | ADC high-level voltage reference input; must not exceed AVDD+0.1 V. |
| 4 | AIN2N | input | Channel 2 negative analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 5 | AIN2P | input | Channel 2 positive analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 6 | AVDD | power_in | Analog power supply for AIN1-4, 4.5-5.5 V. |
| 7 | AVSS | power_in | Analog ground for AIN1-4. |
| 8 | AIN3P | input | Channel 3 positive analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 9 | AIN3N | input | Channel 3 negative analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 10 | VREFH2 | input | ADC high-level voltage reference input; must not exceed AVDD+0.1 V. |
| 11 | VREFL2 | input | ADC low-level voltage reference input; must be connected to AVSS. |
| 12 | NC | unconnected | No internal bonding; connect to AVSS. |
| 13 | AIN4N | input | Channel 4 negative analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 14 | AIN4P | input | Channel 4 positive analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 15 | TEST | input | TEST enable pin; connect to DVSS in PCM and DSD modes per the unused-pin table. |
| 16 | MCLK | input | Master clock input. |
| 17 | TVDD | power_in | Digital I/O buffer and LDO power supply, 1.7-1.98 V when LDOE is L or 3.0-3.6 V when LDOE is H. |
| 18 | DVSS | power_in | Digital ground. |
| 19 | VDD18 | power_in | Digital core power supply, 1.7-1.98 V when LDOE is L; when LDOE is H this pin is the LDO stabilization capacitor connection and cannot supply external circuits. |
| 20 | PDN | input | Reset and power-down pin: L resets and powers down the device, H selects normal operation. |
| 21 | PW0 | input | Power management pin and channel summation select pin 1. |
| 22 | PW1 | input | Power management pin and channel summation select pin 2. |
| 23 | PW2 | input | Power management pin and channel summation select pin 3; also used with PDN for reset. |
| 24 | MSN | input | Master/slave select pin. |
| 25 | BICK/DCLK | bidirectional | Audio serial bit clock: input in PCM slave mode, output in PCM master mode (100 kOhm internal pull-down); DSD clock output in DSD mode. |
| 26 | LRCK/DSDOL1 | bidirectional | Channel clock: input in PCM slave mode, output in PCM master mode (100 kOhm internal pull-down); audio serial data output for AIN1 in DSD mode. |
| 27 | TDMIN/DSDOR1 | input | TDM data input in PCM mode (100 kOhm internal pull-down); audio serial data output for AIN2 in DSD mode. |
| 28 | SDTO1/DSDOL2 | output | Audio serial data output for AIN1 and AIN2 in PCM mode; audio serial data output for AIN3 in DSD mode; output is Low when powered down. |
| 29 | SDTO2/DSDOR2 | output | Audio serial data output for AIN3 and AIN4 in PCM mode; audio serial data output for AIN4 in DSD mode; output is Low when powered down. |
| 30 | OVF | output | Analog input overflow flag output, goes High when any channel overflows (more than -0.3 dBFS in PCM mode). |
| 31 | CKS0/SDA/CDTI | bidirectional | Clock mode select pin; serves as control data I/O (SDA) in I2C mode and control data input (CDTI) in 3-wire serial mode. |
| 32 | CKS1/CAD0_I2C/CSN | input | Clock mode select pin; serves as chip address 0 (CAD0_I2C) in I2C mode and chip select (CSN) in 3-wire serial mode. |
| 33 | CKS2/SCL/CCLK | input | Clock mode select pin; serves as control data clock (SCL) in I2C mode and control data clock (CCLK) in 3-wire serial mode. |
| 34 | CKS3/CAD1 | input | Clock mode select pin; serves as chip address 1 (CAD1) in I2C or 3-wire serial mode. |
| 35 | SLOW/DCKB | input | Slow roll-off digital filter select pin in PCM mode; polarity of DCLK pin in DSD mode. |
| 36 | SD/PMOD | input | Short delay digital filter select pin in PCM mode; DSD phase modulation mode select pin in DSD mode. |
| 37 | DIF0/DSDSEL0 | input | Audio data format select in PCM mode (L: MSB justified, H: I2S); DSD sampling rate control in DSD mode. |
| 38 | DIF1/DSDSEL1 | input | Audio data format select in PCM mode (L: 24-bit, H: 32-bit); DSD sampling rate control in DSD mode. |
| 39 | TDM0 | input | TDM interface format select pin; must be fixed to L when using DSD mode. |
| 40 | TDM1 | input | TDM interface format select pin; must be fixed to L when using DSD mode. |
| 41 | PSN/CAD0_SPI | input | Control mode select pin when I2C pin is H (L: I2C serial control, H: parallel control); chip address 0 for 3-wire serial control when I2C pin is L. |
| 42 | I2C | input | Control mode select pin: L selects 3-wire serial control; H selects I2C serial control or parallel control. |
| 43 | DP | input | DSD mode enable pin: L selects PCM mode, H selects DSD mode. |
| 44 | HPFE/DCKS | input | High-pass filter enable pin in PCM mode (L: disable, H: enable); master clock frequency select in DSD mode. |
| 45 | LDOE | input | LDO enable pin: L disables the internal LDO, H enables it; pulled down internally by 100 kOhm. |
| 46 | ODP | input | Optimal data placement mode enable pin. |
| 47 | AIN1P | input | Channel 1 positive analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 48 | AIN1N | input | Channel 1 negative analog input (full-differential); AIN inputs must stay between AVSS-0.3 V and AVDD+0.3 V and within 10 mA. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Asahi Kasei Microdevices |
| Package | QFN-48-EP(7x7) |
| Category | ADC/DAC/Data Conversion |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Analog (AVDD pin) | AVDD | 4.5 | 5 | 5.5 | V | LDOE pin = L (Note 5) | 8 |
| Digital Interface (TVDD pin), LDOE low | TVDD | 1.7 | 1.8 | 1.98 | V | LDOE pin = L (Note 6) | 8 |
| Digital Core (VDD18 pin) | VDD18 | 1.7 | 1.8 | 1.98 | V | LDOE pin = L | 8 |
| Digital Interface (TVDD pin), LDOE high | TVDD | 3 | 3.3 | 3.6 | V | LDOE pin = H (Note 7) | 8 |
| Voltage Reference "H" voltage (VREFH1-2) | VREFH1-2 | 4.5 | 5 | 5.5 | V | Note 8: must not exceed AVDD+0.1 V | 8 |
| Analog (AVDD pin) absolute maximum | AVDDam | -0.3 | 6 | V | Note 3: voltages with respect to ground | 8 | |
| Digital Interface (TVDD pin) absolute maximum | TVDDam | -0.3 | 4 | V | Note 3: voltages with respect to ground | 8 | |
| Digital Core (VDD18 pin) absolute maximum | VDD18am | -0.3 | 2.5 | V | Note 4: 1.8 V LDO off (LDOE pin = L), external power on VDD18 | 8 | |
| Input Current (any pin except supplies) | IIN | 10 | mA | Any pin except supplies | 8 | ||
| Analog Input Voltage (AIN1-4P, AIN1-4N pins) | VINA | -0.3 | V | AIN1-4P, AIN1-4N pins | 8 | ||
| Digital Input Voltage | VIND | -0.3 | V | 8 | |||
| Ambient Temperature (power applied), back tab connected to VSS | Ta | -40 | 105 | °C | Power applied; back tab connected to VSS | 8 | |
| Ambient Temperature (power applied), back tab open | Ta | -40 | 70 | °C | Power applied; back tab open | 8 | |
| Storage Temperature | Tstg | -65 | 150 | °C | 8 | ||
| Input Voltage (full scale) | 2.7 | 2.8 | 2.9 | Vpp | Note 10: (AINnP)-(AINnN) at ADC full scale | 9 | |
| Resolution | 32 | Bit | 9 | ||||
| S/(N+D) | 100 | 106 | dB | fs= 48 kHz, BW=20 kHz, -1 dBFS | 9 | ||
| Dynamic Range | 110 | 115 | dB | -60 dBFS, A-weighted; Not Sum. mode | 9 | ||
| S/N | 110 | 115 | dB | A-weighted; Not Sum. mode | 9 | ||
| Input Resistance | 8.8 | 10.4 | 12 | kΩ | DSD128/DSD256 values; doubled in DSD 64fs mode | 9 | |
| Interchannel Isolation | 110 | 120 | dB | AIN1-AIN2, AIN3-AIN4 | 9 | ||
| Interchannel Gain Mismatch | 0 | 0.5 | dB | 9 | |||
| Power Supply Current, AVDD+VREFH1/2 (normal operation) | 22 | 29 | mA | PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, TVDD (fs= 48 kHz) | 9 | 12 | mA | PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, TVDD (fs= 96 kHz) | 16 | 21 | mA | PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, TVDD (fs= 192 kHz) | 15 | 20 | mA | PDN pin = H, LDOE pin = H | 9 | ||
| Power Supply Current, power down mode (AVDD+TVDD) | 10 | 100 | µA | PDN pin = L (Note 12) | 9 | ||
| Low-Level Output Voltage | VOL | 0.5 | V | LDOE pin = H (TVDD 3.0-3.6 V); Iout = 100 µA, except SDA pin | 18 | ||
| Low-Level Output Voltage (SDA pin) | VOL | 0.4 | V | LDOE pin = H (TVDD 3.0-3.6 V); SDA pin: Iout = 3 mA | 18 | ||
| Low-Level Output Voltage | VOL | 0.3 | V | LDOE pin = L (TVDD 1.7-1.98 V); Iout = 100 µA, except SDA pin | 18 | ||
| Input Leakage Current | Iin | 10 | µA | 18 | |||
| Master Clock Frequency | fCLK | 2.048 | 49.152 | MHz | CL= 10 pF | 19 | |
| Master Clock Duty Cycle | dCLK | 45 | 55 | % | CL= 10 pF | 19 | |
| LRCK Frequency (Slave mode), Normal Speed mode | fsn | 8 | 54 | kHz | Normal mode (TDM1-0 bits = "00"), CL= 10 pF | 19 | |
| LRCK Frequency (Slave mode), Double Speed mode | fsd | 54 | 108 | kHz | Normal mode (TDM1-0 bits = "00"), CL= 10 pF | 19 | |
| LRCK Frequency (Slave mode), Quad Speed mode | fsq | 108 | 216 | kHz | Normal mode (TDM1-0 bits = "00"), CL= 10 pF | 19 | |
| LRCK Duty Cycle (Slave mode) | Duty | 45 | 55 | % | Slave mode | 19 | |
| BICK Pulse Width Low | tBCKL | 32 | ns | LDOE pin = H; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| BICK Pulse Width High | tBCKH | 32 | ns | LDOE pin = H; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| LRCK Edge to BICK "↑" | tLRB | 25 | ns | LDOE pin = H; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| BICK "↑" to LRCK Edge | tBLR | 25 | ns | LDOE pin = H; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| LRCK to SDTO (MSB) | tLRS | 25 | ns | LDOE pin = H; except I2S mode; CL= 10 pF | 20 | ||
| BICK "↓" to SDTO1/2 | tBSD | 25 | ns | LDOE pin = H; CL= 10 pF | 20 | ||
| BICK Pulse Width Low | tBCKL | 36 | ns | LDOE pin = L; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| BICK Pulse Width High | tBCKH | 36 | ns | LDOE pin = L; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| LRCK Edge to BICK "↑" | tLRB | 30 | ns | LDOE pin = L; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| BICK "↑" to LRCK Edge | tBLR | 30 | ns | LDOE pin = L; normal mode, 8 kHz ≤ fs ≤ 216 kHz; CL= 10 pF | 20 | ||
| LRCK to SDTO (MSB) | tLRS | 30 | ns | LDOE pin = L; except I2S mode; CL= 10 pF | 20 | ||
| BICK "↓" to SDTO1/2 | tBSD | 30 | ns | LDOE pin = L; CL= 10 pF | 20 | ||
| Passband (SHARP ROLL-OFF, fs= 48 kHz) | PB | 0 | 22 | kHz | SD pin = L, SLOW pin = L; +0.001/-0.06 dB | 10 | |
| Stopband (SHARP ROLL-OFF, fs= 48 kHz) | SB | 27.9 | kHz | SD pin = L, SLOW pin = L | 10 | ||
| Stopband Attenuation (SHARP ROLL-OFF, fs= 48 kHz) | SA | 85 | dB | SD pin = L, SLOW pin = L | 10 | ||
| Passband (SLOW ROLL-OFF, fs= 48 kHz) | PB | 0 | 21.9 | kHz | SD pin = L, SLOW pin = H; +0.001/-0.076 dB | 10 | |
| Stopband (SLOW ROLL-OFF, fs= 48 kHz) | SB | 36.5 | kHz | SD pin = L, SLOW pin = H | 10 | ||
| Group Delay Distortion (SHORT DELAY SHARP ROLL-OFF, fs= 48 kHz) | GD | 2.8 | 1/fs | 0 - 20.0 kHz; SD pin = H, SLOW pin = L | 10 | ||
| Group Delay Distortion (SHORT DELAY SLOW ROLL-OFF, fs= 48 kHz) | GD | 1.2 | 1/fs | 0 - 20.0 kHz; SD pin = H, SLOW pin = H | 10 | ||
| Stopband (fs= 384 kHz) | SB | 277.4 | kHz | SD and SLOW pins not applicable | 16 | ||
| Stopband (fs= 768 kHz) | SB | 640.3 | kHz | SD and SLOW pins not applicable | 17 |
CAD (KiCad official)
- Symbol:
AK5554VN - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
ak5554vn-etched.step/ak5554vn-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ak5554vn.step/ak5554vn.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Asahi Kasei Microdevices datasheet (70 pp, sha256
5f7821306c7a7ea1, retrieved 2026-10-29, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).