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SN74HCT574N

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Texas Instruments Flip Flops, PDIP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HCT574N

Texas Instruments · Flip Flops · PDIP-20

SN74HCT574N from Texas Instruments, in a PDIP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable that places the eight 3-state outputs in normal logic state or high-impedance without affecting flip-flop internal operation; VIH min 2 V, VIL max 0.8 V.
2 1D input Data input for flip-flop 1, latched on the low-to-high transition of CLK.
3 2D input Data input for flip-flop 2, latched on the low-to-high transition of CLK.
4 3D input Data input for flip-flop 3, latched on the low-to-high transition of CLK.
5 4D input Data input for flip-flop 4, latched on the low-to-high transition of CLK.
6 5D input Data input for flip-flop 5, latched on the low-to-high transition of CLK.
7 6D input Data input for flip-flop 6, latched on the low-to-high transition of CLK.
8 7D input Data input for flip-flop 7, latched on the low-to-high transition of CLK.
9 8D input Data input for flip-flop 8, latched on the low-to-high transition of CLK.
10 GND power_in Ground pin.
11 CLK input Clock input; the eight flip-flops enter data on its low-to-high transition.
12 8Q tri_state 3-state output of flip-flop 8, with ±6 mA drive at 5 V.
13 7Q tri_state 3-state output of flip-flop 7, with ±6 mA drive at 5 V.
14 6Q tri_state 3-state output of flip-flop 6, with ±6 mA drive at 5 V.
15 5Q tri_state 3-state output of flip-flop 5, with ±6 mA drive at 5 V.
16 4Q tri_state 3-state output of flip-flop 4, with ±6 mA drive at 5 V.
17 3Q tri_state 3-state output of flip-flop 3, with ±6 mA drive at 5 V.
18 2Q tri_state 3-state output of flip-flop 2, with ±6 mA drive at 5 V.
19 1Q tri_state 3-state output of flip-flop 1, with ±6 mA drive at 5 V.
20 VCC power_in Supply voltage, 4.5 V to 5.5 V recommended, with a 0.1 µF bypass capacitor close to the pin.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-20
Category Logic ICs
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High-level output voltage VOH 4.4 4.499 V VI = VIH or VIL, IOH = −20 μA, VCC 4.5 V 5
High-level output voltage VOH 3.84 4.3 V VI = VIH or VIL, IOH = −6 mA, VCC 4.5 V 5
Low-level output voltage VOL 0.001 0.1 V VI = VIH or VIL, IOL = 20 μA, VCC 4.5 V 5
Low-level output voltage VOL 0.17 0.33 V VI = VIH or VIL, IOL = 6 mA, VCC 4.5 V 5
Input leakage current II -1000 0.1 1000 nA VI = VCC or 0, VCC 5.5 V 5
Off-state (high-impedance) output current IOZ -5 0.01 5 μA VO = VCC or 0, VCC 5.5 V 5
Quiescent supply current ICC 8 80 μA VI = VCC or 0, IO = 0, VCC 5.5 V 5
Supply current increase per TTL-level input ΔICC 1.4 2.9 mA One input at 0.5 V or 2.4 V, other inputs at 0 or VCC, VCC 5.5 V 5
Input capacitance Ci 3 10 pF VCC 4.5 V to 5.5 V 5
Clock frequency fclock 24 MHz VCC 4.5 V 5
Clock frequency fclock 27 MHz VCC 5.5 V 5
Pulse duration, CLK high or low tw 20 ns VCC 4.5 V 5
Pulse duration, CLK high or low tw 18 ns VCC 5.5 V 5
Setup time, data before CLK↑ tsu 25 ns VCC 4.5 V 5
Setup time, data before CLK↑ tsu 23 ns VCC 5.5 V 5
Hold time, data after CLK↑ th 5 ns VCC 4.5 V 5
Maximum clock frequency fmax 24 36 MHz CL = 50 pF, VCC 4.5 V 5
Maximum clock frequency fmax 27 40 MHz CL = 50 pF, VCC 5.5 V 5
Propagation delay CLK to Q tpd 30 45 ns CL = 50 pF, VCC 4.5 V 5
Propagation delay CLK to Q tpd 25 41 ns CL = 50 pF, VCC 5.5 V 5
Output enable time OE to Q ten 26 38 ns CL = 50 pF, VCC 4.5 V 5
Output enable time OE to Q ten 23 34 ns CL = 50 pF, VCC 5.5 V 5
Output disable time OE to Q tdis 23 38 ns CL = 50 pF, VCC 4.5 V 5
Output disable time OE to Q tdis 22 34 ns CL = 50 pF, VCC 5.5 V 5
Output transition time tt 10 15 ns CL = 50 pF, VCC 4.5 V 5
Output transition time tt 9 14 ns CL = 50 pF, VCC 5.5 V 5
Propagation delay CLK to Q tpd 40 66 ns CL = 150 pF, VCC 4.5 V 6
Propagation delay CLK to Q tpd 35 60 ns CL = 150 pF, VCC 5.5 V 6
Output enable time OE to Q ten 34 59 ns CL = 150 pF, VCC 4.5 V 6
Output enable time OE to Q ten 29 78 ns CL = 150 pF, VCC 5.5 V 6
Output transition time tt 18 53 ns CL = 150 pF, VCC 4.5 V 6
Output transition time tt 16 48 ns CL = 150 pF, VCC 5.5 V 6
Supply voltage VCC 4.5 5 5.5 V 4
High-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V 4
Input voltage VI 0 V Maximum is VCC 4
Output voltage VO 0 V Maximum is VCC 4
Input transition rise/fall time Δt/Δv 500 ns 4
Operating free-air temperature TA -40 85 °C SN74HCT574 4
Supply voltage range VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < 0 or VI > VCC 4
Output clamp current IOK -20 20 mA VO < 0 or VO > VCC 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND ICC/IGND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature range Tstg -65 150 °C 4
Junction-to-ambient thermal resistance RθJA 84.6 °C/W N (PDIP) 20-pin package 4
Junction-to-case (top) thermal resistance RθJC(top) 72.5 °C/W N (PDIP) 20-pin package 4
Junction-to-board thermal resistance RθJB 65.3 °C/W N (PDIP) 20-pin package 4
Junction-to-top characterization parameter ψJT 55.3 °C/W N (PDIP) 20-pin package 4
Junction-to-board characterization parameter ψJB 65.2 °C/W N (PDIP) 20-pin package 4

CAD (KiCad official)

  • Symbol: SN74HCT574N
  • Footprint: Package_DIP:DIP-20_W7.62mm
  • 3D model: PDIP-20 (KiCad packages3D, STEP)
  • 3D model files: sn74hct574n-etched.step / sn74hct574n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hct574n.step / sn74hct574n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 ef06d23eec4f0073, retrieved 2026-10-30, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF