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ATSAM4SA16BA-MU

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Microchip Tech Pre-ordered MCUs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersatsam4sa16ba-mufactory-2.0.0extractor-text

Changed since verified ATSAM4SA16BA-MU

by Ray · last 31 Oct 2026 · 1 record · files changed since
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: ATSAM4SA16BA-MU · QFN-64-EP(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 1269-page datasheet
  • ✓distributor: lcsc C614616, digikey ATSAM4SA16BA-MU-ND, mouser 556-ATSAM4SA16BA-MU
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-sizbipgd/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! atsam4sa16ba-mu.kicad_sym✓ atsam4sa16ba-mu.kicad_mod✓ atsam4sa16ba-mu.step
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Symbol & Footprint

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Contents

README

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ATSAM4SA16BA-MU

Microchip Tech · Pre-ordered MCUs · QFN-64-EP(9x9)

ATSAM4SA16BA-MU from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADVREF input ADC, DAC and analog comparator reference voltage input.
2 GND power_in Ground.
3 PB0/AD4 bidirectional PIO line PB0 shared with ADC analog input AD4.
4 PB1/AD5 bidirectional PIO line PB1 shared with ADC analog input AD5.
5 PB2/AD6 bidirectional PIO line PB2 shared with ADC analog input AD6.
6 PB3/AD7 bidirectional PIO line PB3 shared with ADC analog input AD7.
7 VDDIN power_in Voltage regulator input, ADC, DAC and analog comparator supply, 1.62 to 3.6 V.
8 VDDOUT power_out Voltage regulator output.
9 PA17/PGMD5/AD0 bidirectional PIO line PA17 shared with FFPI data PGMD5 and ADC input AD0.
10 PA18/PGMD6/AD1 bidirectional PIO line PA18 shared with FFPI data PGMD6 and ADC input AD1.
11 PA21/PGMD9/AD8 bidirectional PIO line PA21 shared with FFPI data PGMD9 and ADC input AD8.
12 VDDCORE power_in Core, first flash rail and embedded memories/peripherals supply, 1.08 to 1.32 V.
13 PA19/PGMD7/AD2 bidirectional PIO line PA19 shared with FFPI data PGMD7 and ADC input AD2.
14 PA22/PGMD10/AD9 bidirectional PIO line PA22 shared with FFPI data PGMD10 and ADC input AD9.
15 PA23/PGMD11 bidirectional PIO line PA23 shared with FFPI data PGMD11.
16 PA20/PGMD8/AD3 bidirectional PIO line PA20 shared with FFPI data PGMD8 and ADC input AD3.
17 GND power_in Ground.
18 VDDIO power_in Peripheral I/O lines, second flash rail, USB transceiver, backup part and oscillator supply, 1.62 to 3.6 V.
19 PA16/PGMD4 bidirectional PIO line PA16 shared with FFPI data PGMD4.
20 PA15/PGMD3 bidirectional PIO line PA15 shared with FFPI data PGMD3.
21 PA14/PGMD2 bidirectional PIO line PA14 shared with FFPI data PGMD2.
22 PA13/PGMD1 bidirectional PIO line PA13 shared with FFPI data PGMD1.
23 PA24/PGMD12 bidirectional PIO line PA24 shared with FFPI data PGMD12.
24 VDDCORE power_in Core, first flash rail and embedded memories/peripherals supply, 1.08 to 1.32 V.
25 PA25/PGMD13 bidirectional PIO line PA25 shared with FFPI data PGMD13.
26 PA26/PGMD14 bidirectional PIO line PA26 shared with FFPI data PGMD14.
27 PA12/PGMD0 bidirectional PIO line PA12 shared with FFPI data PGMD0.
28 PA11/PGMM3 bidirectional PIO line PA11 shared with FFPI programming mode input PGMM3.
29 PA10/PGMM2 bidirectional PIO line PA10 shared with FFPI programming mode input PGMM2.
30 PA9/PGMM1 bidirectional PIO line PA9 shared with FFPI programming mode input PGMM1.
31 PA8/XOUT32/PGMM0 bidirectional PIO line PA8 shared with 32 kHz crystal output XOUT32 and FFPI mode input PGMM0.
32 PA7/XIN32/PGMNVALID bidirectional PIO line PA7 shared with 32 kHz crystal input XIN32 and FFPI data direction output PGMNVALID.
33 TDI/PB4 bidirectional JTAG test data in shared with PIO line PB4.
34 PA6/PGMNOE bidirectional PIO line PA6 shared with FFPI programming read input PGMNOE (active low).
35 PA5/PGMRDY bidirectional PIO line PA5 shared with FFPI programming ready output PGMRDY.
36 PA4/PGMNCMD bidirectional PIO line PA4 shared with FFPI programming command input PGMNCMD (active low).
37 PA27/PGMD15 bidirectional PIO line PA27 shared with FFPI data PGMD15.
38 PA28 bidirectional General-purpose PIO line PA28.
39 NRST bidirectional Microcontroller reset, active low input/output.
40 TST input Test select input; low at power-up selects normal mode, high selects test or FFPI mode, with internal pull-down of about 15 kOhm.
41 PA29 bidirectional General-purpose PIO line PA29.
42 PA30 bidirectional General-purpose PIO line PA30.
43 PA3 bidirectional General-purpose PIO line PA3.
44 PA2/PGMEN2 bidirectional PIO line PA2 shared with FFPI programming enable input PGMEN2.
45 VDDIO power_in Peripheral I/O lines, second flash rail, USB transceiver, backup part and oscillator supply, 1.62 to 3.6 V.
46 GND power_in Ground.
47 PA1/PGMEN1 bidirectional PIO line PA1 shared with FFPI programming enable input PGMEN1.
48 PA0/PGMEN0 bidirectional PIO line PA0 shared with FFPI programming enable input PGMEN0.
49 TDO/TRACESWO/PB5 bidirectional JTAG test data out or asynchronous trace output, shared with PIO line PB5.
50 JTAGSEL input JTAG selection input, active high.
51 TMS/SWDIO/PB6 bidirectional JTAG test mode select or serial wire I/O, shared with PIO line PB6.
52 PA31 bidirectional General-purpose PIO line PA31.
53 TCK/SWCLK/PB7 bidirectional JTAG test clock or serial wire clock, shared with PIO line PB7.
54 VDDCORE power_in Core, first flash rail and embedded memories/peripherals supply, 1.08 to 1.32 V.
55 ERASE/PB12 bidirectional Flash erase input shared with PIO line PB12.
56 DDM/PB10 bidirectional USB full-speed data minus shared with PIO line PB10.
57 DDP/PB11 bidirectional USB full-speed data plus shared with PIO line PB11.
58 VDDIO power_in Peripheral I/O lines, second flash rail, USB transceiver, backup part and oscillator supply, 1.62 to 3.6 V.
59 PB13/DAC0 bidirectional PIO line PB13 shared with DAC analog output DAC0.
60 GND power_in Ground.
61 XOUT/PB8 bidirectional Main oscillator output shared with PIO line PB8.
62 XIN/PGMCK/PB9 bidirectional Main oscillator input shared with FFPI clock PGMCK and PIO line PB9.
63 PB14/DAC1 bidirectional PIO line PB14 shared with DAC analog output DAC1.
64 VDDPLL power_in Powers PLLA, PLLB, the fast RC and the 3 to 20 MHz oscillator, 1.08 to 1.32 V.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(9x9)
Category Embedded Processors & Controllers
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDDIO supply voltage range VDDIO 1.62 3.6 V I/O lines, flash 2nd rail, USB transceiver, backup part, 32 kHz oscillator 27
VDDIN supply voltage range VDDIN 1.62 3.6 V Voltage regulator input, ADC, DAC and analog comparator supply 27
VDDCORE supply voltage range VDDCORE 1.08 1.32 V Core, first flash rail, embedded memories and peripherals 27
VDDPLL supply voltage range VDDPLL 1.08 1.32 V PLLA, PLLB, fast RC and 3 to 20 MHz oscillator 27
Operating temperature range -40 85 °C Industrial, ATSAM4SA16BA-MU (QFN64) 1220
Maximum CPU speed 120 MHz 1
Default regulator output voltage VDDOUT 1.2 V default output voltage 28

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC before performing the calculation, making the base address for the calculation word-aligned. ̶ Note: To generate the address of an instruction, the constant based on the value of the PC must be 118

CAD (KiCad official)

  • Symbol: ATSAM4SA16BA-MU
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: atsam4sa16ba-mu-etched.step / atsam4sa16ba-mu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); atsam4sa16ba-mu.step / atsam4sa16ba-mu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (1269 pp, sha256 64941c58dfa3899c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF