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STM8S105K4T6C

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by Ray

STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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STM8S105K4T6C

STMicroelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

STM8S105K4T6C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NRST bidirectional Active-low reset input/output. Bidirectional pin - asserted low by internal reset sources (POR, watchdog, SWIM) and can be driven low externally to reset the device. Includes an internal pull-up.
2 PA1/OSC_IN bidirectional Port A bit 1 GPIO with weak pull-up option, slow (2 MHz) push-pull or open-drain output. Alternate function: resonator/crystal input (OSC_IN) for the external clock oscillator.
3 PA2/OSC_OUT bidirectional Port A bit 2 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Alternate function: resonator/crystal output (OSC_OUT) for the external oscillator.
4 VSS power_in Digital ground reference for the STM8 core and digital peripherals.
5 VCAP power_in Output of the internal 1.8 V regulator that supplies the core logic. Requires an external stabilization capacitor (typically 1 µF ceramic) to VSS. Do not connect to any external supply.
6 VDD power_in Digital power supply (2.95 V to 5.5 V) for the STM8 core and digital peripherals. Decouple locally with a 100 nF ceramic capacitor to VSS.
7 VDDIO_1 power_in I/O power supply (2.95 V to 5.5 V) for one bank of GPIO output buffers. Should be tied to VDD in typical single-supply designs and decoupled with a 100 nF ceramic capacitor.
8 PF4/AIN12 bidirectional Port F bit 4 GPIO with weak pull-up option, slow (2 MHz) push-pull or open-drain output. Alternate function: ADC analog input channel 12 (AIN12). Has an active pull-up during reset phase; floats after reset release.
9 VDDA power_in Analog power supply (2.95 V to 5.5 V) for the 10-bit ADC and internal analog reference. Recommend a ferrite or LC filter from VDD and a 100 nF + 1 µF decoupling network to VSSA.
10 VSSA power_in Analog ground reference for the ADC and analog circuitry. Should be joined to VSS at a single star point near the MCU for best ADC accuracy.
11 PB5/AIN5/[I2C_SDA] bidirectional Port B bit 5 GPIO with external interrupt capability, weak pull-up option, slow (2 MHz) push-pull or open-drain output. Default alternate function: ADC analog input 5 (AIN5). Remap alternate (AFR6): I²C serial data (I2C_SDA).
12 PB4/AIN4/[I2C_SCL] bidirectional Port B bit 4 GPIO with external interrupt capability, weak pull-up option, slow (2 MHz) push-pull or open-drain output. Default alternate: ADC analog input 4 (AIN4). Remap alternate (AFR6): I²C serial clock (I2C_SCL).
13 PB3/AIN3/[TIM1_ETR] bidirectional Port B bit 3 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Default alternate: ADC analog input 3 (AIN3). Remap alternate (AFR5): TIM1 external trigger input (TIM1_ETR).
14 PB2/AIN2/[TIM1_CH3N] bidirectional Port B bit 2 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Default alternate: ADC analog input 2 (AIN2). Remap alternate (AFR5): TIM1 complementary channel 3 output (TIM1_CH3N).
15 PB1/AIN1/[TIM1_CH2N] bidirectional Port B bit 1 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Default alternate: ADC analog input 1 (AIN1). Remap alternate (AFR5): TIM1 complementary channel 2 output (TIM1_CH2N).
16 PB0/AIN0/[TIM1_CH1N] bidirectional Port B bit 0 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Default alternate: ADC analog input 0 (AIN0). Remap alternate (AFR5): TIM1 complementary channel 1 output (TIM1_CH1N).
17 PE5/SPI_NSS bidirectional Port E bit 5 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Alternate function: SPI master/slave select (SPI_NSS).
18 PC1/TIM1_CH1/UART2_CK bidirectional Port C bit 1 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast (10 MHz) programmable push-pull or open-drain output. Alternate functions: TIM1 channel 1 (TIM1_CH1) or UART2 synchronous clock (UART2_CK).
19 PC2/TIM1_CH2 bidirectional Port C bit 2 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Alternate function: TIM1 channel 2 (TIM1_CH2).
20 PC3/TIM1_CH3 bidirectional Port C bit 3 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Alternate function: TIM1 channel 3 (TIM1_CH3).
21 PC4/TIM1_CH4 bidirectional Port C bit 4 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable open-drain output. Alternate function: TIM1 channel 4 (TIM1_CH4).
22 PC5/SPI_SCK bidirectional Port C bit 5 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Alternate function: SPI clock (SPI_SCK).
23 PC6/SPI_MOSI bidirectional Port C bit 6 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Alternate function: SPI master-out/slave-in (SPI_MOSI).
24 PC7/SPI_MISO bidirectional Port C bit 7 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Alternate function: SPI master-in/slave-out (SPI_MISO).
25 PD0/TIM3_CH2/[TIM1_BKIN]/[CLK_CCO] bidirectional Port D bit 0 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Default alternate: TIM3 channel 2 (TIM3_CH2). Remap alternates: TIM1 break input (TIM1_BKIN, AFR3) or configurable clock output (CLK_CCO, AFR2).
26 PD1/SWIM bidirectional Port D bit 1 GPIO with external interrupt capability, high-sink drive, fast programmable output (fast as default state after reset). Alternate function: Single Wire Interface Module (SWIM) - the ST programming/debug interface used with ST-LINK. In input pull-up during reset and after reset release.
27 PD2/TIM3_CH1/[TIM2_CH3] bidirectional Port D bit 2 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Default alternate: TIM3 channel 1 (TIM3_CH1). Remap alternate (AFR1): TIM2 channel 3 (TIM2_CH3).
28 PD3/TIM2_CH2/[ADC_ETR] bidirectional Port D bit 3 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Default alternate: TIM2 channel 2 (TIM2_CH2). Remap alternate (AFR0): ADC external trigger (ADC_ETR).
29 PD4/TIM2_CH1/[BEEP] bidirectional Port D bit 4 GPIO with external interrupt capability, high-sink drive, weak pull-up option, fast programmable push-pull or open-drain output. Default alternate: TIM2 channel 1 (TIM2_CH1). Remap alternate (AFR7): BEEP output.
30 PD5/UART2_TX bidirectional Port D bit 5 GPIO with external interrupt capability, weak pull-up option, slow (2 MHz) push-pull or open-drain output. Alternate function: UART2 data transmit (UART2_TX).
31 PD6/UART2_RX bidirectional Port D bit 6 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Alternate function: UART2 data receive (UART2_RX).
32 PD7/TLI/[TIM1_CH4] bidirectional Port D bit 7 GPIO with external interrupt capability, weak pull-up option, slow push-pull or open-drain output. Default alternate: top level interrupt (TLI). Remap alternate (AFR4): TIM1 channel 4 (TIM1_CH4).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Ordering variants

Same part, different packaging or reel option.

  • STM8S105K4T6C
  • STM8S105K4T6CK6T6
  • STM8S105K4T6CK6T6C
  • STM8S105K4T6CK4U6
  • STM8S105K4T6CK6U6
  • STM8S105K4T6CS4T6
  • STM8S105K4T6CS6T6
  • STM8S105K4T6CC4T6
  • STM8S105K4T6CC6T6

CAD (KiCad official)

  • Symbol: STM8S105K4T6C
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (99 pp, sha256 9cd29ad29b7c0ce9, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF