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AD9248BSTZ-20

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Analog Devices Analog To Digital Converters (ADCs), LQFP-64(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9248BSTZ-20

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-64(7x7)

AD9248BSTZ-20 from Analog Devices, in a LQFP-64(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground for the ADC.
2 VIN+_A power_in Positive analog input pin for Channel A, supporting a differential input span of 1 V p-p to 2 V p-p.
3 VIN-_A power_in Negative analog input pin for Channel A, complementary to VIN+_A.
4 AGND power_in Analog ground for the ADC.
5 AVDD power_in Analog power supply, specified from 2.7 V to 3.6 V.
6 REFT_A passive Differential reference (+) for Channel A.
7 REFB_A passive Differential reference (-) for Channel A.
8 VREF power_in Voltage reference input/output pin for the internal reference.
9 SENSE input Reference mode selection pin.
10 REFB_B passive Differential reference (-) for Channel B.
11 REFT_B passive Differential reference (+) for Channel B.
12 AVDD power_in Analog power supply, specified from 2.7 V to 3.6 V.
13 AGND power_in Analog ground for the ADC.
14 VIN-_B power_in Negative analog input pin for Channel B, complementary to VIN+_B.
15 VIN+_B power_in Positive analog input pin for Channel B, supporting a differential input span of 1 V p-p to 2 V p-p.
16 AGND power_in Analog ground for the ADC.
17 AVDD power_in Analog power supply, specified from 2.7 V to 3.6 V.
18 CLK_B input Clock input pin for Channel B.
19 DCS input Enables duty cycle stabilizer (DCS) mode.
20 DFS input Data output format select: low for offset binary, high for twos complement.
21 PDWN_B input Power-down selection for Channel B: logic 0 enables the channel, logic 1 powers it down with outputs static, not High-Z.
22 OEB_B input Output enable for Data Bus B: logic 0 enables the bus, logic 1 sets outputs to High-Z.
23 D0_B (LSB) output Channel B data output bit 0 (least significant bit).
24 D1_B output Channel B data output bit 1.
25 D2_B output Channel B data output bit 2.
26 D3_B output Channel B data output bit 3.
27 D4_B output Channel B data output bit 4.
28 DRGND power_in Digital output ground.
29 DRVDD power_in Digital output driver supply, to be decoupled to DRGND with a minimum 0.1 μF capacitor (0.1 μF in parallel with 10 μF recommended).
30 D5_B output Channel B data output bit 5.
31 D6_B output Channel B data output bit 6.
32 D7_B output Channel B data output bit 7.
33 D8_B output Channel B data output bit 8.
34 D9_B output Channel B data output bit 9.
35 D10_B output Channel B data output bit 10.
36 D11_B output Channel B data output bit 11.
37 D12_B output Channel B data output bit 12.
38 D13_B (MSB) output Channel B data output bit 13 (most significant bit).
39 OTR_B output Out-of-range indicator for Channel B.
40 DRGND power_in Digital output ground.
41 DRVDD power_in Digital output driver supply, to be decoupled to DRGND with a minimum 0.1 μF capacitor.
42 D0_A (LSB) output Channel A data output bit 0 (least significant bit).
43 D1_A output Channel A data output bit 1.
44 D2_A output Channel A data output bit 2.
45 D3_A output Channel A data output bit 3.
46 D4_A output Channel A data output bit 4.
47 D5_A output Channel A data output bit 5.
48 D6_A output Channel A data output bit 6.
49 D7_A output Channel A data output bit 7.
50 D8_A output Channel A data output bit 8.
51 D9_A output Channel A data output bit 9.
52 DRVDD power_in Digital output driver supply, to be decoupled to DRGND with a minimum 0.1 μF capacitor.
53 DRGND power_in Digital output ground.
54 D10_A output Channel A data output bit 10.
55 D11_A output Channel A data output bit 11.
56 D12_A output Channel A data output bit 12.
57 D13_A (MSB) output Channel A data output bit 13 (most significant bit).
58 OTR_A output Out-of-range indicator for Channel A.
59 OEB_A input Output enable for Data Bus A: logic 0 enables the bus, logic 1 sets outputs to High-Z.
60 PDWN_A input Power-down selection for Channel A: logic 0 enables the channel, logic 1 powers it down with outputs static, not High-Z.
61 MUX_SELECT input Data multiplexed mode control; a high setting disables output data multiplexed mode.
62 SHARED_REF input Shared reference control: low for independent reference mode, high for shared reference mode.
63 CLK_A input Clock input pin for Channel A.
64 AVDD power_in Analog power supply, specified from 2.7 V to 3.6 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64(7x7)
Category ADC/DAC/Data Conversion
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage AVDD AVDD 2.7 3 3.6 V 3
Digital output driver supply DRVDD DRVDD 2.25 3 3.6 V 3
Offset error -1.3 0.2 1.3 % FSR 25°C 3
Gain error -2.2 0.25 2.2 % FSR Full temperature range 3
Differential nonlinearity (DNL) DNL -1 0.6 1 LSB 25°C 3
Integral nonlinearity (INL) INL -4.5 2.3 4.5 LSB 25°C 3
Output voltage error (1 V mode) -35 5 35 mV Full temperature range 3
Offset error matching (nonshared reference mode) -1.56 0.19 1.56 % FSR 25°C 4
Offset error matching (shared reference mode) -1.56 0.19 1.56 % FSR 25°C 4
Gain error matching (nonshared reference mode) -1.43 0.07 1.43 % FSR 25°C 4
Gain error matching (shared reference mode) -0.06 0.01 0.06 % FSR 25°C 4
Maximum conversion rate 20 MSPS Full temperature range 7
Output delay (tPD) tPD 2 3.5 6 ns Measured from clock 50% to data 50% with 5 pF load 7
AVDD to AGND AVDD -0.3 3.9 V 8
DRVDD to DRGND DRVDD -0.3 3.9 V 8
AGND to DRGND -0.3 0.3 V 8
AVDD to DRVDD -3.9 3.9 V 8
Operating temperature -40 85 °C 8
Junction temperature 150 °C 8
Lead temperature 300 °C 10 sec 8
Storage temperature -65 150 °C 8
Minimum conversion rate 1 MSPS Full temperature range 7
Supply current IAVDD IAVDD 60 mA Full temperature range 3
Supply current IDRVDD IDRVDD 5 mA Full temperature range 3
Power supply rejection ratio (PSRR) PSRR 0.01 % FSR Full temperature range 3
DC input power consumption 180 mW DC input at maximum clock rate 3
Standby power 2 mW Full temperature range 3
Offset error temperature drift 2 ppm/°C Full temperature range 3
Gain error temperature drift 12 ppm/°C Full temperature range 3
Output voltage error (0.5 V mode) 2.5 mV Full temperature range 3
Load regulation 0.8 mV @ 1.0 mA, Full temperature range 3
Load regulation 0.1 mV @ 0.5 mA, Full temperature range 3
Differential nonlinearity (DNL) DNL 0.65 LSB Full temperature range 3
Integral nonlinearity (INL) INL 2.7 LSB Full temperature range 3
Input referred noise 2.1 LSB rms 25°C, input span 1 V 3
Input referred noise 1.05 LSB rms 25°C, input span 2.0 V 3
Analog input span 1 V p-p Input span = 1.0 V, Full temperature range 3
Analog input span 2 V p-p Input span = 2.0 V, Full temperature range 3
Input capacitance 7 pF Full temperature range 3
Reference input resistance 7 kΩ Full temperature range 3
Signal-to-noise ratio (SNR) SNR 73.4 dB fINPUT = 2.4 MHz, Full temperature range 5
Signal-to-noise and distortion ratio (SINAD) SINAD 73 dB fINPUT = 2.4 MHz, Full temperature range 5
Effective number of bits (ENOB) ENOB 11.8 Bits fINPUT = 2.4 MHz, Full temperature range 5
Worst harmonic (second or third) 86 dBc fINPUT = 2.4 MHz, Full temperature range 5
Signal-to-noise ratio (SNR) SNR 72.9 dB fINPUT = 9.7 MHz, Full temperature range 5
Signal-to-noise ratio (SNR) SNR 72.7 dB fINPUT = 19.6 MHz, Full temperature range 5
Signal-to-noise ratio (SNR) SNR 71.5 dB fINPUT = 35 MHz, Full temperature range 5
Clock period 50 ns Full temperature range 7
Clock pulse-width high 15 ns Full temperature range 7
Clock pulse-width low 15 ns Full temperature range 7
Pipeline delay (latency) 7 Cycles Full temperature range 7
Aperture delay (tA) tA 1 ns Full temperature range 7
Aperture uncertainty (tJ) tJ 0.5 ps rms Full temperature range 7
Wake-up time 2.5 ms 0.1 μF and 10 μF on REFT and REFB 7
Out-of-range recovery time 2 Cycles Full temperature range 7
Thermal resistance junction to ambient (64-lead LQFP) θJA 54 °C/W 64-lead LQFP, 4-layer board, still air 8

CAD (KiCad official)

  • Symbol: AD9248BSTZ-20
  • Footprint: Package_QFP:LQFP-64_7x7mm_P0.4mm
  • 3D model: LQFP-64(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9248bstz-20-etched.step / ad9248bstz-20-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9248bstz-20.step / ad9248bstz-20.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (48 pp, sha256 1391d00e48ba5ecf, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF