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TPS7A4701QRGWTQ1
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Texas Instruments Linear Voltage Regulators (LDO), VQFN-20-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS7A4701QRGWTQ1
Texas Instruments · Linear Voltage Regulators (LDO) · VQFN-20-EP(5x5)
TPS7A4701QRGWTQ1 from Texas Instruments, in a VQFN-20-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulator output; a capacitor of at least 10 µF must be tied to ground for stability, 47 µF ceramic recommended. |
| 2 | NC | unconnected | No connect; can be left open or tied to any voltage between GND and IN. |
| 3 | SENSE/FB | input | Control-loop error amplifier input; SENSE (connected to OUT) in ANY-OUT mode, or FB when output is set with external resistors. |
| 4 | 6P4V2 | input | When connected to GND adds 6.4 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 5 | 6P4V1 | input | When connected to GND adds 6.4 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 6 | 3P2V | input | When connected to GND adds 3.2 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 7 | GND | power_in | Ground. |
| 8 | 1P6V | input | When connected to GND adds 1.6 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 9 | 0P8V | input | When connected to GND adds 0.8 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 10 | 0P4V | input | When connected to GND adds 0.4 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 11 | 0P2V | input | When connected to GND adds 0.2 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 12 | 0P1V | input | When connected to GND adds 0.1 V to the nominal output voltage; connect only GND, leave floating if unused. |
| 13 | EN | input | Enable pin; device is enabled when voltage exceeds VEN(HI), tie to IN if enable not required. |
| 14 | NR | passive | Noise-reduction pin; capacitor of at least 10 nF to GND required for stability, 1 µF recommended to minimize noise. |
| 15 | IN | power_in | Input supply (3 V to 35 V); capacitor of at least 1 µF to ground required for stability, 10 µF recommended. |
| 16 | IN | power_in | Input supply (3 V to 35 V); capacitor of at least 1 µF to ground required for stability, 10 µF recommended. |
| 17 | NC | unconnected | No connect; can be left open or tied to any voltage between GND and IN. |
| 18 | NC | unconnected | No connect; can be left open or tied to any voltage between GND and IN. |
| 19 | NC | unconnected | No connect; can be left open or tied to any voltage between GND and IN. |
| 20 | OUT | power_out | Regulator output; a capacitor of at least 10 µF must be tied to ground for stability, 47 µF ceramic recommended. |
| 21 | PowerPAD | power_in | Exposed pad internally connected to GND; connect to a large-area ground plane. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-20-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | VI | 3 | 35 | V | 5 | ||
| Output voltage | VO | 1.4 | 34 | V | 5 | ||
| Output capacitor | COUT | 10 | µF | 5 | |||
| Enable pin voltage | VEN | 0 | V | 5 | |||
| Output current | IO | 0 | 1 | A | 5 | ||
| IN pin to GND pin | -0.4 | 36 | V | 4 | |||
| EN pin to GND pin | -0.4 | 36 | V | 4 | |||
| EN pin to IN pin | -36 | 0.4 | V | 4 | |||
| OUT pin to GND pin | -0.4 | 36 | V | 4 | |||
| NR pin to GND pin | -0.4 | 36 | V | 4 | |||
| SENSE/FB pin to GND pin | -0.4 | 36 | V | 4 | |||
| 0P1V pin to GND pin | -0.4 | 36 | V | 4 | |||
| 0P2V pin to GND pin | -0.4 | 36 | V | 4 | |||
| 0P4V pin to GND pin | -0.4 | 36 | V | 4 | |||
| 0P8V pin to GND pin | -0.4 | 36 | V | 4 | |||
| 1P6V pin to GND pin | -0.4 | 36 | V | 4 | |||
| 3P2V pin to GND pin | -0.4 | 36 | V | 4 | |||
| 6P4V1 pin to GND pin | -0.4 | 36 | V | 4 | |||
| 6P4V2 pin to GND pin | -0.4 | 36 | V | 4 | |||
| Operating virtual junction temperature | TJ | -40 | 145 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage range | VI | 3 | 35 | V | 6 | ||
| Nominal VO accuracy | -1 | 1 | %VO | TJ = 25°C, COUT = 20 µF | 6 | ||
| Overall VO accuracy | -2.5 | 2.5 | %VO | VO(nom) + 1.0 V ≤ VI ≤ 35 V, 0 mA ≤ IO ≤ 1 A, COUT = 20 µF | 6 | ||
| Output voltage range (ANY-OUT option) | VO | 1.4 | 20.5 | V | COUT = 20 µF, using ANY-OUT option | 6 | |
| Output voltage range (adjustable option) | VO | 1.4 | 34 | V | COUT = 20 µF, using adjustable option | 6 | |
| Enable high-level voltage | V+EN(HI) | 2 | V | 6 | |||
| Enable low-level voltage | V+EN(LO) | 0 | 0.4 | V | 6 | ||
| Current limit | I(CL) | 1 | 1.26 | A | VO = 90% VO(nom) | 6 | |
| Operating junction temperature | TJ | -40 | 145 | °C | 6 | ||
| Undervoltage lockout threshold, rising | VUVLO | 2.67 | V | VI rising | 6 | ||
| Undervoltage lockout threshold, falling | VUVLO | 2.5 | V | VI falling | 6 | ||
| Reference voltage | V(REF) | 1.4 | V | V(REF) = V(FB) | 6 | ||
| Undervoltage lockout hysteresis | VUVLO(HYS) | 177 | mV | 6 | |||
| Noise reduction pin voltage | VNR | 1.4 | V | In adjustable mode only | 6 | ||
| Line regulation | ΔVO(ΔVI) | 0.092 | %VO | VO(nom) + 1.0 V ≤ VI ≤ 35 V | 6 | ||
| Load regulation | ΔVO(ΔIO) | 0.3 | %VO | 0 mA ≤ IO ≤ 1 A | 6 | ||
| Dropout voltage at 0.5 A | V(DO) | 216 | mV | VI = 95% VO(nom), IO = 0.5 A | 6 | ||
| Dropout voltage at 1 A | V(DO) | 307 | 450 | mV | VI = 95% VO(nom), IO = 1 A | 6 | |
| Ground pin current at no load | I(GND) | 0.58 | 1 | mA | IO = 0 mA | 6 | |
| Ground pin current at 1 A | I(GND) | 6.1 | mA | IO = 1 A | 6 | ||
| Enable pin current | I(EN) | 0.78 | 2 | µA | VEN = VI | 6 | |
| Enable pin current at 35 V | I(EN) | 0.81 | 2 | µA | VI = VEN = 35 V | 6 | |
| Shutdown supply current | I(SHDN) | 2.55 | 8 | µA | VEN = 0.4 V | 6 | |
| Shutdown supply current at 35 V | I(SHDN) | 3.04 | 60 | µA | VEN = 0.4 V, VI = 35 V | 6 | |
| Feedback pin current | I(FB) | 350 | nA | 6 | |||
| Power-supply rejection ratio | PSRR | 78 | dB | VI = 16 V, VO(nom) = 15 V, COUT = 50 µF, IO = 500 mA, CNR = 1 µF, f = 1 kHz | 6 | ||
| Output noise voltage (VO(nom) = 1.4 V) | Vn | 4.17 | µVRMS | VI = 3 V, VO(nom) = 1.4 V, COUT = 50 µF, CNR = 1 µF, BW = 10 Hz to 100 kHz | 6 | ||
| Output noise voltage (VO(nom) = 5 V) | Vn | 4.67 | µVRMS | VIN = 6 V, VO(nom) = 5 V, COUT = 50 µF, CNR = 1 µF, BW = 10 Hz to 100 kHz | 6 | ||
| Thermal shutdown temperature | Tsd | 170 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown reset temperature | Tsd | 150 | °C | Reset, temperature decreasing | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 31.1 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 21.1 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 10.2 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 0.2 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 10.2 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1.9 | °C/W | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | input and output capacitor, and to the LDO ground pin, must also be as close to each other as possible and connected by a wide, component-side, copper surface. The use of vias and long traces to creat | 20 |
CAD (KiCad official)
- Symbol:
TPS7A4701QRGWTQ1 - Footprint:
Package_DFN_QFN:QFN-20-1EP_5x5mm_P0.65mm_EP3.35x3.35mm - 3D model: VQFN-20-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps7a4701qrgwtq1-etched.step/tps7a4701qrgwtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps7a4701qrgwtq1.step/tps7a4701qrgwtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
e90305f495dd4c68, retrieved 2026-10-30, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).