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CKS32F103CBT6

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by adom

CKS Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscks32f103cbt6factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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CKS32F103CBT6

CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

CKS32F103CBT6 from CKS, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup supply 1.8-3.6 V that powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is off.
2 PC13-TAMPER-RTC bidirectional GPIO PC13 (also TAMPER-RTC) fed through the supply switch limited to 3 mA; as an output it is limited to 2 MHz, 30 pF load, and cannot source current such as an LED.
3 PC14-OSC32_IN bidirectional GPIO PC14 or LSE oscillator input OSC32_IN; as an output it is limited to 2 MHz, 30 pF load and no LED drive (3 mA supply switch limit).
4 PC15-OSC32_OUT bidirectional GPIO PC15 or LSE oscillator output OSC32_OUT; as an output it is limited to 2 MHz, 30 pF load and no LED drive (3 mA supply switch limit).
5 OSC_IN input External high-speed oscillator input (4-16 MHz crystal/resonator, or 8 MHz external clock); after reset this pin is OSC_IN and can be reassigned by software to PD0.
6 OSC_OUT output External high-speed oscillator output; after reset this pin is OSC_OUT and can be reassigned by software to PD1, where output mode is limited to 50 MHz.
7 NRST bidirectional Active-low reset with internal pull-up (30-50 kΩ); input pulses shorter than 100 ns are filtered and pulses longer than 300 ns are not filtered.
8 VSSA power_in Analog ground for ADC, reset block, RC oscillators and PLL; must be connected to VSS.
9 VDDA power_in Analog supply 2.0-3.6 V for ADC, reset block, RC oscillators and PLL; ADC use requires at least 2.4 V and VDDA must be connected to VDD.
10 PA0-WKUP bidirectional GPIO PA0 (standard I/O, not 5 V tolerant) with alternate functions WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR.
11 PA1 bidirectional GPIO PA1 (standard I/O) with alternate functions USART2_RTS, ADC12_IN1 and TIM2_CH2.
12 PA2 bidirectional GPIO PA2 (standard I/O) with alternate functions USART2_TX, ADC12_IN2 and TIM2_CH3.
13 PA3 bidirectional GPIO PA3 (standard I/O) with alternate functions USART2_RX, ADC12_IN3 and TIM2_CH4.
14 PA4 bidirectional GPIO PA4 (standard I/O) with alternate functions SPI1_NSS, USART2_CK and ADC12_IN4.
15 PA5 bidirectional GPIO PA5 (standard I/O) with alternate functions SPI1_SCK and ADC12_IN5.
16 PA6 bidirectional GPIO PA6 (standard I/O) with alternate functions SPI1_MISO, ADC12_IN6, TIM3_CH1 and TIM1_BKIN.
17 PA7 bidirectional GPIO PA7 (standard I/O) with alternate functions SPI1_MOSI, ADC12_IN7, TIM3_CH2 and the complementary timer channel printed as TIMI_CHIN.
18 PB0 bidirectional GPIO PB0 (standard I/O) with alternate functions ADC12_IN8, TIM3_CH3 and TIM1_CH2N.
19 PB1 bidirectional GPIO PB1 (standard I/O) with alternate functions ADC12_IN9, TIM3_CH4 and TIM1_CH3N.
20 PB2/BOOT1 bidirectional 5 V tolerant GPIO PB2 that also serves as the BOOT1 boot-mode configuration pin.
21 PB10 bidirectional 5 V tolerant GPIO PB10 with alternate functions I2C2_SCL, USART3_TX and TIM2_CH3.
22 PB11 bidirectional 5 V tolerant GPIO PB11 with alternate functions I2C2_SDA, USART3_RX and TIM2_CH4.
23 VSS_1 power_in Digital ground pin (VSS) and voltage reference for all device voltages.
24 VDD_1 power_in Digital supply 2.0-3.6 V that powers the I/O pins and the internal regulator.
25 PB12 bidirectional 5 V tolerant GPIO PB12 with alternate functions SPI2_NSS, I2C2_SMBAI, USART3_CK and TIM1_BKIN.
26 PB13 bidirectional 5 V tolerant GPIO PB13 with alternate functions SPI2_SCK, USART3_CTS and TIM1_CH1N.
27 PB14 bidirectional 5 V tolerant GPIO PB14 with alternate functions SPI2_MISO, USART3_RTS and TIM1_CH2N.
28 PB15 bidirectional 5 V tolerant GPIO PB15 with alternate functions SPI2_MOSI and TIM1_CH3N.
29 PA8 bidirectional 5 V tolerant GPIO PA8 with alternate functions USART1_CK, TIM1_CH1 and MCO.
30 PA9 bidirectional 5 V tolerant GPIO PA9 with alternate functions USART1_TX and TIM1_CH2.
31 PA10 bidirectional 5 V tolerant GPIO PA10 with alternate functions USART1_RX and TIM1_CH3.
32 PA11 bidirectional 5 V tolerant GPIO PA11 with alternate functions USART1_CTS, USBDM, CANRX and TIM1_CH4.
33 PA12 bidirectional 5 V tolerant GPIO PA12 with alternate functions USART1_RTS, USBDP, CANTX and TIM1_ETR.
34 PA13 bidirectional 5 V tolerant pin PA13 used as the JTMS/SWDIO serial-wire debug data line.
35 VSS_2 power_in Digital ground pin (VSS).
36 VDD_2 power_in Digital supply 2.0-3.6 V that powers the I/O pins and the internal regulator.
37 PA14 bidirectional 5 V tolerant pin PA14 used as the JTCK/SWCLK serial-wire debug clock.
38 PA15 bidirectional 5 V tolerant GPIO PA15 that can also serve as JTDI, TIM2_CH1_ETR and SPI1_NSS (remapped).
39 PB3 bidirectional 5 V tolerant GPIO PB3 that can also serve as JTDO/TRACESWO, TIM2_CH2 and SPI1_SCK.
40 PB4 bidirectional 5 V tolerant GPIO PB4 that can also serve as JNTRST, TIM3_CH1 and SPI1_MISO.
41 PB5 bidirectional GPIO PB5 with alternate functions I2C1_SMBAI, TIM3_CH2 and SPI1_MOSI.
42 PB6 bidirectional 5 V tolerant GPIO PB6 with alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX.
43 PB7 bidirectional 5 V tolerant GPIO PB7 with alternate functions I2C1_SDA, TIM4_CH2 and USART1_RX.
44 BOOT0 input Boot mode selection input; the datasheet gives its input voltage range as 0 to 5.5 V.
45 PB8 bidirectional 5 V tolerant GPIO PB8 with alternate functions TIM4_CH3, I2C1_SCL and CANRX.
46 PB9 bidirectional 5 V tolerant GPIO PB9 (printed as 'P89' in the datasheet) with alternate functions TIM4_CH4, I2C1_SDA and CANTX.
47 VSS_3 power_in Digital ground pin (VSS).
48 VDD_3 power_in Digital supply 2.0-3.6 V that powers the I/O pins and the internal regulator.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating supply voltage (VDD, I/O) VDD 2 3.6 V CPU frequency 72 MHz 2
Operating ambient temperature (suffix 6) TA -40 85 °C Product suffix 6 2
Operating junction temperature TJ -40 125 °C 2
USB transceiver startup time tSTARTUP 1 μs 50
USB operating voltage VDD 3 3.6 V 51
Differential input sensitivity VDI 0.2 V I(USBDP,USBDM) 51
Differential common mode range VCM 0.8 2.5 V Includes VDI range 51
Single-ended receiver threshold VSE 1.3 2 V 51
Static output low level VOL 0.3 V 1.5kΩ RL to 3.6V 51
Static output high level VOH 2.8 3.6 V 15kΩ RL to VSS 51
USB rise time tr 4 20 ns CL ≤ 50pF 51
USB fall time tf 4 20 ns CL ≤ 50pF 51
USB rise/fall time matching trfm 90 110 % tr / tf 51
Output signal crossover voltage VCRS 1.3 2 V 51
ADC supply voltage VDDA 2.4 3.6 V 52
ADC positive reference voltage VREF+ 2.4 V Max printed as VDDA 52
ADC input voltage current from VREF+ IVREF 160 220 μA 52
ADC clock frequency fADC 0.6 14 MHz 52
ADC sampling rate fS 0.05 1 MHz 52
External trigger frequency fTRIG 823 kHz fADC=14MHz 52
External trigger frequency fTRIG 17 1/fADC 52
External input impedance RAIN 50 kΩ 52
Sampling switch resistance RADC 1 kΩ 52
Internal sample and hold capacitance CADC 8 pF 52
Sampling time tS 0.107 17.1 μs fADC=14MHz 52
Sampling time tS 1.5 239.5 1/fADC 52
ADC power-up time tSTAB 0 0 1 μs 52
Total conversion time (including sampling) tCONV 1 18 μs fADC=14MHz 52
Total conversion time (including sampling) tCONV 14 252 1/fADC Sampling tS + successive approximation 12.5 52

CAD (KiCad official)

  • Symbol: CKS32F103CBT6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cks32f103cbt6-etched.step / cks32f103cbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f103cbt6.step / cks32f103cbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (64 pp, sha256 221001e6207f4f99, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF