M40SZ100WMQ6F from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	NC	unconnected	Not connected internally.
2	NC	unconnected	Not connected internally.
3	RST	output	Open-drain power-on reset output, guaranteed low by VPFD and held low for tREC (40 to 200 ms) after VCC exceeds VPFD, needing a pull-up resistor to VCC.
4	NC	unconnected	Not connected internally.
5	RSTIN	input	Reset input that generates a reset identical to a power-cycle reset, internally pulled up to VCC through a 100 kΩ resistor, with pulses shorter than 50 ns ignored.
6	PFO	output	Power-fail output that goes low when PFI is below the 1.25 V threshold and is low during battery backup.
7	VBAT	power_in	Backup battery supply input, 2.5 V min, 3.0 V typ, 3.5 V max.
8	VSS	power_in	Ground.
9	ECON	output	Conditioned chip enable output that follows E in normal operation with less than 15 ns delay and is forced inactive to write-protect the SRAM when VCC is out of tolerance.
10	E	input	Chip enable input from the processor, gated to produce ECON.
11	BL	output	Open-drain battery low output asserted when the battery voltage is below approximately 2.5 V, needing a pull-up resistor to VCC.
12	PFI	input	Power-fail input compared with the internal 1.25 V reference (1.225 to 1.275 V threshold at VCC = 3 V); connect to VSS if unused.
13	NC	unconnected	Not connected internally.
14	VOUT	power_out	Supply output to the SRAM, switched from VCC (drop under 0.3 V, up to 100 mA) or from the battery below VSO (up to 100 µA).
15	NC	unconnected	Not connected internally.
16	VCC	power_in	Supply voltage input, 2.7 to 3.6 V operating, absolute maximum 4.6 V.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-16
Category	Power Management ICs
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Storage temperature (VCC off)	TSTG	-55		125	°C	VCC off	14
Lead solder temperature for 10 seconds	TSLD			260	°C	for 10 seconds	14
Input or output voltages	VIO	-0.3			V	upper limit printed as VCC +0.3 V	14
Supply voltage	VCC	-0.3		4.6	V		14
Output current	IO			20	mA		14
Power dissipation	PD			1	W		14
Supply voltage	VCC	2.7		3.6	V	ambient operating temperature -40 to 85 °C	15
Ambient operating temperature	TA	-40		85	°C	VCC = 2.7 to 3.6 V	15
Input capacitance	CIN			7	pF	sampled only; at 25 °C, f = 1 MHz	15
Output capacitance	COUT			10	pF	outputs deselected; at 25 °C, f = 1 MHz	15
Supply current	ICC			0.5	mA	outputs open	16
Data retention mode current	ICCDR		50	200	nA	VOUT and ECON open	16
Input leakage current	ILI	-1		1	μA	0 V ≤ VIN ≤ VCC	16
Input leakage current (PFI)	ILI	-25	2	25	nA		16
Output leakage current	ILO	-1		1	μA	0 V ≤ VOUT ≤ VCC	16
VOUT current (active)	IOUT1			100	mA	VOUT > VCC, 0.3	16
VOUT current (battery backup)	IOUT2			100	μA	VOUT > VBAT, 0.3	16
Battery voltage	VBAT	2.5	3	3.5	V		16
Input low voltage	VIL	-0.3			V		16
Output high voltage	VOH	2.4			V	IOH = -1.0 mA	16
VOH battery backup	VOHB	2.5	2.9	3.5	V	IOUT2 = -1.0 μA	16
Output low voltage	VOL			0.4	V	IOL = 3.0 mA	16
Output low voltage (open drain)	VOL			0.4	V	IOL = 10 mA	16
Power-fail deselect voltage	VPFD	2.55	2.6	2.7	V		16
PFI input threshold	VPFI	1.225	1.25	1.275	V	VCC = 3 V	16
PFI hysteresis		20		70	mV	PFI rising	16
VCC fall time, VPFD (max) to VPFD (min)	tF			300	μs	VPFD (max) to VPFD (min)	10
VCC fall time, VPFD (min) to VSS	tFB			10	μs	VPFD (min) to VSS	10
PFI to PFO propagation delay	tPFD	15		25	μs		10
VCC rise time, VPFD(min) to VPFD(max)	tR			10	μs	VPFD(min) to VPFD(max)	10
Chip enable propagation delay (low or high)	tEPD			15	ns	low or high	10
VCC rise time, VSS to VPFD(min)	tRB			1	μs	VSS to VPFD(min)	10
Chip enable recovery	tCER	40		120	ms		10
VPFD (max) to RST high	tREC	40		200	ms		10
Write protect time	tWPT	40		200	μs		10
RSTIN low to RSTIN high	tRLRH	200			ns		11
RSTIN high to RST high	tR1HRH	40		200	ms	CL = 50 pF	11

CAD (KiCad official)

Symbol: M40SZ100WMQ6F
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SO-16 (KiCad packages3D, STEP)
3D model files: m40sz100wmq6f-etched.step / m40sz100wmq6f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); m40sz100wmq6f.step / m40sz100wmq6f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (20 pp, sha256 f4778d7158439f43, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

M40SZ100WMQ6F

Verified M40SZ100WMQ6F

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3D Model

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