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MP6610GS-Z

Public Made by Adom

by adom

Monolithic Power Systems Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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MP6610GS-Z

Monolithic Power Systems · Gate Drivers · SOIC-8

MP6610GS-Z from Monolithic Power Systems, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BST passive Bootstrap pin: connect a 100nF capacitor between BST and OUT; BST is rated VIN to (VIN + 5.7V).
2 VIN power_in Input supply voltage, rated 4V to 55V for the SOIC-8 package (absolute maximum -0.3V to +65V); decouple VIN to GND with a 100nF or greater ceramic capacitor.
3 OUT output Half-bridge output terminal (absolute maximum -0.7V to +65V); a 100nF capacitor connects it to BST.
4 GND power_in System ground.
5 nFAULT output Open-drain fault indication output that goes logic low on over-current protection, over-temperature protection, or open load, and requires an external pull-up resistor.
6 ISET passive Current configuration pin: a resistor from ISET to ground sets the current limit and ISET voltage scaling (absolute maximum -0.3V to +5.5V).
7 IN input Half-bridge input: pull high to drive the output high and low to force the output low; pin is pulled down via an internal resistor.
8 EN input Half-bridge enable input: pull high to turn the half-bridge driver on and low to turn it off; pin is pulled down via an internal resistor.

Key specifications

Parameter Value
Manufacturer Monolithic Power Systems
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input supply voltage VIN 4 55 V SOIC-8 package 4
Quiescent current IQ 1.3 5 mA VIN = 24V, VEN = 0V, no load current 4
High-side MOSFET (HS-FET) output on resistance RDS(ON)_HS 100 120 mΩ VIN = 24V, IOUT = 1A, TJ = 25°C 4
Low-side MOSFET (LS-FET) output on resistance RDS(ON)_LS 120 150 mΩ VIN = 24V, IOUT = 1A, TJ = 25°C 4
Body diode forward voltage VF 1.1 V IOUT = 1A 4
Input logic high threshold VIN_HIGH 2 V 4
Input logic low threshold VIN_LOW 0.8 V 4
Logic high input current IIN_HIGH 6 14 µA VIN_HIGH = 5V 4
Logic low input current IIN_LOW 4 µA VIN_LOW = 0.8V 4
nFault output low voltage VOUT_LOW 0.8 V IOUT = 5mA 4
Output high leakage current IOUT_LK 1 µA VOUT = 3.3V 4
Over-voltage protection (OVP) rising threshold VOVP_RISING 55 65 V 4
Open-load detection (OLD) threshold, VOUT low VOLD 1 1.5 V VOUT is low 4
Open-load detection (OLD) threshold, VOUT high VOLD 21.5 23.2 V VOUT is high, VIN = 24V 4
ISET current, HS-FET source IISET 69 90 118 µA/A HS-FET source, IOUT = 1A 5
ISET current, HS-FET sink IISET 82 102 131 µA/A HS-FET sink, IOUT = 1A 5
ISET current, LS-FET source IISET 83 104 130 µA/A LS-FET source, IOUT = 1A 5
ISET current, LS-FET sink IISET 82 103 129 µA/A LS-FET sink, IOUT = 1A 5
Current trip voltage VTRIP 1.4 1.5 1.6 V At ISET pin 5
Supply voltage VIN -0.3 65 V 3
Output voltage VOUT -0.7 65 V 3
ISET pin voltage ISET -0.3 5.5 V 3
All other pins to GND -0.3 6.5 V All other pins to GND 3
Storage temperature TSTG -55 150 °C 3
Junction temperature TJ 150 °C 3
Lead temperature (solder) 260 °C Solder 3
ESD human body model (HBM) 2 kV Human body model (HBM) 3
ESD charged device model (CDM) -750 750 V Charged device model (CDM) 3
Supply voltage (SOIC-8) VIN 4 55 V SOIC-8 package 3
Output current IOUT -3 3 A 3
Operating junction temperature TJ -40 125 °C 3
UVLO rising threshold VUVLO_RISING 4.1 V 4
UVLO threshold hysteresis VUVLO_HYS 300 mV 4
OVP threshold hysteresis VOVP_HYS 900 mV 4
Over-current protection (OCP) trip level, sink IOCP1 3 A Sink 4
Over-current protection (OCP) trip level, source IOCP2 3 A Source 4
OCP deglitch time (not tested in production) tOCP 1 µs 4
OCP retry time tOCP_RETRY 1.6 ms 4
Thermal shutdown TSD 165 °C 4
Thermal shutdown hysteresis ΔTSD_HYS 15 °C 4
Current open-load detection (OLD) IOLD 90 µA 4
Internal pull-down resistance RPD 530 kΩ 4
Off time tOFF 16.5 µs After VTRIP is reached 5
Blanking time tBLANK 1 µs 5
Thermal resistance junction-to-case (SOIC-8) θJC 45 °C/W SOIC-8 package; JESD51-7, 4-layer PCB 3

CAD (KiCad official)

  • Symbol: MP6610GS-Z
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: mp6610gs-z-etched.step / mp6610gs-z-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mp6610gs-z.step / mp6610gs-z.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Monolithic Power Systems datasheet (16 pp, sha256 8ef37175aa799bb6, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF