component
NCP711ASN500T1G
Public Made by Adomby adom
onsemi Linear Voltage Regulators (LDO), TSOP-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownNCP711ASN500T1G
onsemi · Linear Voltage Regulators (LDO) · TSOP-5
NCP711ASN500T1G from onsemi, in a TSOP-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Power supply input pin; the recommended input voltage range is 2.7 V to 18 V. |
| 2 | GND | power_in | Ground pin. |
| 3 | EN | input | Enable input (high = enabled, low = disabled); if tied to IN or left unconnected the device is enabled and no pull-up resistor is required. |
| 4 | NC | unconnected | Not internally connected on the fixed-voltage version A; this pin can be tied to the ground plane to improve thermal dissipation. |
| 5 | OUT | power_out | LDO output pin, regulated to the nominal 5.0 V version output with ±1% accuracy from −40 °C to +85 °C and designed for up to 100 mA output current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSOP-5 |
| Category | Power Management ICs |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Recommended Input Voltage | VIN | 2.7 | 18 | V | 4 | ||
| Output Voltage Accuracy | VOUT | -1 | 1 | % | TJ = −40°C to +85°C | 4 | |
| Output Voltage Accuracy | VOUT | -1 | 2 | % | TJ = −40°C to +125°C | 4 | |
| Line Regulation | VO(VI) | 0.2 | %VOUT | VIN = VOUT−NOM + 1 V to 18 V and VIN ≥ 2.7 V | 4 | ||
| Load Regulation | VO(IO) | 0.4 | %VOUT | IOUT = 0.1 mA to 100 mA | 4 | ||
| Quiescent Current (version A) | IQ | 1.3 | 2.5 | A | VIN = VOUT−NOM + 1 V to 18 V, IOUT = 0 mA | 4 | |
| Ground Current | IGND | 325 | 450 | A | IOUT = 100 mA | 4 | |
| Shutdown Current | ISHDN | 0.35 | 1.5 | A | VEN = 0 V, IOUT = 0 mA, VIN = 18 V | 4 | |
| Output Current Limit | IOLIM | 140 | 250 | 450 | mA | VOUT = VOUT−NOM − 100 mV | 4 |
| Short Circuit Current | IOSC | 140 | 250 | 450 | mA | VOUT = 0 V | 4 |
| Dropout Voltage | VDO | 215 | 355 | mV | IOUT = 100 mA | 4 | |
| EN Threshold | VEN-TH | 0.7 | 0.9 | 1.05 | V | VEN rising | 5 |
| EN Hysteresis | VEN-HY | 0.01 | 0.1 | 0.2 | V | VEN falling | 5 |
| EN Internal Pull-up Current | IEN-PU | 0.01 | 0.3 | 1 | A | VEN = 1 V, VIN = 5.5 V | 5 |
| EN Input Leakage Current | IEN-LK | -1 | 0.05 | 1 | A | VEN = 18 V, VIN = 18 V | 5 |
| Start-up time | tSTART | 300 | 600 | 1000 | s | VOUT−NOM > 3.3 V | 5 |
| Internal UVLO Threshold | VIUL-TH | 1.6 | 1.95 | 2.6 | V | Ramp VIN up until output is turned on | 5 |
| Internal UVLO Hysteresis | VIUL-HY | 0.05 | 0.2 | 0.3 | V | Ramp VIN down until output is turned off | 5 |
| Operating Junction Temperature Range | TJ | -40 | 125 | °C | Electrical characteristics temperature range (table header) | 4 | |
| VIN Voltage | VIN | -0.3 | 22 | V | 4 | ||
| VOUT Voltage | VOUT | -0.3 | V | 4 | |||
| EN Voltage | VEN | -0.3 | V | 4 | |||
| ADJ Voltage | VFB/ADJ | -0.3 | 5.5 | V | 4 | ||
| Maximum Junction Temperature | TJ(MAX) | 150 | °C | 4 | |||
| Storage Temperature | TSTG | -55 | 150 | °C | 4 | ||
| ESD Capability, Human Body Model | ESDHBM | 2000 | V | ANSI/ESDA/JEDEC JS-001, EIA/JESD22-A114 | 4 | ||
| ESD Capability, Charged Device Model | ESDCDM | 1000 | V | ANSI/ESDA/JEDEC JS-002, EIA/JESD22-C101 | 4 | ||
| Thermal Resistance, Junction-to-Air | RthJA | 147 | °C/W | TSOP-5, JEDEC board 1S2P, no airflow | 4 | ||
| Thermal Resistance, Junction-to-Case (top) | RthJCt | 82 | °C/W | TSOP-5 | 4 | ||
| Thermal Resistance, Junction-to-Board (top) | RthJBt | 113 | °C/W | TSOP-5 | 4 | ||
| Thermal Characterization Parameter, Junction-to-Case (top) | PsiJCt | 22 | °C/W | TSOP-5 | 4 | ||
| Thermal Characterization Parameter, Junction-to-Board [FEM] | PsiJB | 113 | °C/W | TSOP-5 | 4 |
CAD (KiCad official)
- Symbol:
NCP711ASN500T1G - Footprint:
Package_SO:TSOP-5_1.65x3.05mm_P0.95mm - 3D model: TSOP-5 (KiCad packages3D, STEP)
- 3D model files:
ncp711asn500t1g-etched.step/ncp711asn500t1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ncp711asn500t1g.step/ncp711asn500t1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (12 pp, sha256
e38ab168e681b63f, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).