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DS100BR410SQ

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Texas Instruments Signal Buffers, Repeaters, Splitters, WQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DS100BR410SQ

Texas Instruments · Signal Buffers, Repeaters, Splitters · WQFN-48-EP(7x7)

DS100BR410SQ from Texas Instruments, in a WQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN_0+ input Non-inverting CML differential input to the channel 0 equalizer, with an on-chip 100 Ω terminating resistor between IN_0+ and IN_0-.
2 IN_0- input Inverting CML differential input to the channel 0 equalizer, with an on-chip 100 Ω terminating resistor between IN_0+ and IN_0-.
3 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
4 IN_1+ input Non-inverting CML differential input to the channel 1 equalizer, with an on-chip 100 Ω terminating resistor between IN_1+ and IN_1-.
5 IN_1- input Inverting CML differential input to the channel 1 equalizer, with an on-chip 100 Ω terminating resistor between IN_1+ and IN_1-.
6 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
7 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
8 IN_2+ input Non-inverting CML differential input to the channel 2 equalizer, with an on-chip 100 Ω terminating resistor between IN_2+ and IN_2-.
9 IN_2- input Inverting CML differential input to the channel 2 equalizer, with an on-chip 100 Ω terminating resistor between IN_2+ and IN_2-.
10 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
11 IN_3+ input Non-inverting CML differential input to the channel 3 equalizer, with an on-chip 100 Ω terminating resistor between IN_3+ and IN_3-.
12 IN_3- input Inverting CML differential input to the channel 3 equalizer, with an on-chip 100 Ω terminating resistor between IN_3+ and IN_3-.
13 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
14 BST_1 input Equalizer boost select bit 1 (LVCMOS 2.5 V) for all channels in pin mode, internally pulled high; see Table 1 for the boost levels.
15 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
16 CS input SMBus chip select (3.3 V LVCMOS tolerant); high enables access to the SMBus registers, low disables them.
17 SDC input SMBus clock input (3.3 V LVCMOS tolerant); an external pull-up may be required depending on the host.
18 SDA bidirectional SMBus data input / open-drain output (3.3 V LVCMOS tolerant); an external pull-up resistor is required, 1 kΩ to 5 kΩ.
19 VOD_SEL input Four-level analog input setting the CML output differential amplitude: tie to VDD = 1.2 Vp-p, open = 1.0 Vp-p, 20 kΩ to GND = 800 mVp-p, tie to GND = 600 mVp-p.
20 DE_SEL input Four-level analog input setting output de-emphasis: tie to VDD = -9 dB, open = -6 dB, 20 kΩ to GND = -3 dB, tie to GND = 0 dB.
21 PIN_MODE input Pin mode control (2.5 V LVCMOS): high selects pin control mode, low selects SMBus control mode; internally pulled high.
22 GND power_in Ground reference.
23 BST_0 input Equalizer boost select bit 0 (2.5 V LVCMOS) for all channels in pin mode, internally pulled low; see Table 1 for the boost levels.
24 GND power_in Ground reference.
25 OUT_3- output Inverting CML differential output from the channel 3 driver, with an on-chip 100 Ω terminating resistor between OUT_3+ and OUT_3-.
26 OUT_3+ output Non-inverting CML differential output from the channel 3 driver, with an on-chip 100 Ω terminating resistor between OUT_3+ and OUT_3-.
27 GND power_in Ground reference.
28 OUT_2- output Inverting CML differential output from the channel 2 driver, with an on-chip 100 Ω terminating resistor between OUT_2+ and OUT_2-.
29 OUT_2+ output Non-inverting CML differential output from the channel 2 driver, with an on-chip 100 Ω terminating resistor between OUT_2+ and OUT_2-.
30 GND power_in Ground reference.
31 GND power_in Ground reference.
32 OUT_1- output Inverting CML differential output from the channel 1 driver, with an on-chip 100 Ω terminating resistor between OUT_1+ and OUT_1-.
33 OUT_1+ output Non-inverting CML differential output from the channel 1 driver, with an on-chip 100 Ω terminating resistor between OUT_1+ and OUT_1-.
34 GND power_in Ground reference.
35 OUT_0- output Inverting CML differential output from the channel 0 driver, with an on-chip 100 Ω terminating resistor between OUT_0+ and OUT_0-.
36 OUT_0+ output Non-inverting CML differential output from the channel 0 driver, with an on-chip 100 Ω terminating resistor between OUT_0+ and OUT_0-.
37 BST_2 input Equalizer boost select bit 2 (2.5 V LVCMOS) for all channels in pin mode, internally pulled high; see Table 1 for the boost levels.
38 EN3 input Enable input for channel 3 (2.5 V LVCMOS): high for normal operation, low selects standby; internally pulled high.
39 SD3 output Signal detect output for channel 3 (2.5 V LVCMOS): high when a signal is detected, low when no signal is detected.
40 EN2 input Enable input for channel 2 (2.5 V LVCMOS): high for normal operation, low selects standby; internally pulled high.
41 SD2 output Signal detect output for channel 2 (2.5 V LVCMOS): high when a signal is detected, low when no signal is detected.
42 EN1 input Enable input for channel 1 (2.5 V LVCMOS): high for normal operation, low selects standby; internally pulled high.
43 SD1 output Signal detect output for channel 1 (2.5 V LVCMOS): high when a signal is detected, low when no signal is detected.
44 EN0 input Enable input for channel 0 (2.5 V LVCMOS): high for normal operation, low selects standby; internally pulled high.
45 SD0 output Signal detect output for channel 0 (2.5 V LVCMOS): high when a signal is detected, low when no signal is detected.
46 VDD power_in Supply pin, VDD = 2.5 V ±5% (2.375 V to 2.625 V).
47 OOB_DIS input Out-of-band disable input (2.5 V LVCMOS): high disables OOB, low enables it; internally pulled low.
48 RES unconnected Reserved, do not connect.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-48-EP(7x7)
Category Interface
Pins 49

CAD (KiCad official)

  • Symbol: DS100BR410SQ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: WQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ds100br410sq-etched.step / ds100br410sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds100br410sq.step / ds100br410sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 8e94d1ce609c1af9, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF