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PIC32MX150F128D-I
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Microchip Tech Microcontroller Units (MCUs/MPUs/SOCs), QFN-44-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownPIC32MX150F128D-I
Microchip Tech · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-44-EP(8x8)
PIC32MX150F128D-I from Microchip Tech, in a QFN-44-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RPB9/SDA1/CTED4/PMD3/RB9 | bidirectional | PORTB I/O RB9 with remappable RP9, I2C1 data SDA1, CTMU edge input CTED4 and PMP data bit PMD3. |
| 2 | RPC6/PMA1/RC6 | bidirectional | PORTC I/O RC6 with remappable RPC6 and PMP address bit PMA1. |
| 3 | RPC7/PMA0/RC7 | bidirectional | PORTC I/O RC7 with remappable RPC7 and PMP address bit PMA0. |
| 4 | RPC8/PMA5/RC8 | bidirectional | PORTC I/O RC8 with remappable RPC8 and PMP address bit PMA5. |
| 5 | RPC9/CTED7/PMA6/RC9 | bidirectional | PORTC I/O RC9 with remappable RPC9, CTMU edge input CTED7 and PMP address bit PMA6. |
| 6 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |
| 7 | VCAP | passive | CPU logic filter capacitor connection; needs a low-ESR (3 ohm) capacitor to ground and must not be connected to VDD. |
| 8 | PGED2/RPB10/CTED11/PMD2/RB10 | bidirectional | PORTB I/O RB10 with ICSP data channel 2 PGED2, remappable RPB10, CTED11 and PMP data bit PMD2. |
| 9 | PGEC2/RPB11/PMD1/RB11 | bidirectional | PORTB I/O RB11 with ICSP clock channel 2 PGEC2, remappable RPB11 and PMP data bit PMD1. |
| 10 | AN12/PMD0/RB12 | bidirectional | PORTB I/O RB12 with ADC analog input AN12 and PMP data bit PMD0. |
| 11 | AN11/RPB13/CTPLS/PMRD/RB13 | bidirectional | PORTB I/O RB13 with analog input AN11, remappable RPB13, CTMU pulse output CTPLS and PMP read strobe PMRD. |
| 12 | PGED4/TMS/PMA10/RA10 | bidirectional | PORTA I/O RA10 with ICSP data channel 4 PGED4, JTAG test mode select TMS and PMP address bit PMA10. |
| 13 | PGEC4/TCK/CTED8/PMA7/RA7 | bidirectional | PORTA I/O RA7 with ICSP clock channel 4 PGEC4, JTAG clock TCK, CTED8 and PMP address bit PMA7. |
| 14 | CVREFOUT/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 | bidirectional | PORTB I/O RB14 with comparator reference output CVREFOUT, analog input AN10, comparator input C3INB, remappable RPB14, SPI1 clock SCK1, CTED5 and PMP write strobe PMWR. |
| 15 | AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 | bidirectional | PORTB I/O RB15 with analog input AN9, comparator input C3INA, remappable RPB15, SPI2 clock SCK2, CTED6 and PMP chip select PMCS1. |
| 16 | AVSS | power_in | Ground reference for analog modules; must be connected even if the ADC is not used. |
| 17 | AVDD | power_in | Positive supply for analog modules; must be connected at all times. |
| 18 | MCLR | input | Master Clear active-low Reset input, also used for device programming and debugging. |
| 19 | VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 | power_in | PORTA I/O RA0 with ADC/comparator voltage reference high input VREF+/CVREF+, analog input AN0, comparator input C3INC, remappable RPA0 and CTED1. |
| 20 | VREF-/CVREF-/AN1/RPA1/CTED2/RA1 | power_in | PORTA I/O RA1 with voltage reference low input VREF-/CVREF-, analog input AN1, remappable RPA1 and CTED2. |
| 21 | PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 | bidirectional | PORTB I/O RB0 with ICSP data channel 1 PGED1, analog input AN2, comparator inputs C1IND/C2INB/C3IND and remappable RPB0. |
| 22 | PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 | bidirectional | PORTB I/O RB1 with ICSP clock channel 1 PGEC1, analog input AN3, comparator inputs C1INC/C2INA, remappable RPB1 and CTED12. |
| 23 | AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 | bidirectional | PORTB I/O RB2 with analog input AN4, comparator inputs C1INB/C2IND, remappable RPB2, I2C2 data SDA2 and CTED13. |
| 24 | AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 | bidirectional | PORTB I/O RB3 with analog input AN5, comparator inputs C1INA/C2INC, RTCC alarm output, remappable RPB3 and I2C2 clock SCL2. |
| 25 | AN6/RPC0/RC0 | bidirectional | PORTC I/O RC0 with analog input AN6 and remappable RPC0. |
| 26 | AN7/RPC1/RC1 | bidirectional | PORTC I/O RC1 with analog input AN7 and remappable RPC1. |
| 27 | AN8/RPC2/PMA2/RC2 | bidirectional | PORTC I/O RC2 with analog input AN8, remappable RPC2 and PMP address bit PMA2. |
| 28 | VDD | power_in | Positive supply for peripheral logic and I/O pins. |
| 29 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |
| 30 | OSC1/CLKI/RPA2/RA2 | bidirectional | Oscillator crystal input / external clock input CLKI (ST buffer in RC mode, CMOS otherwise), shared with PORTA RA2 and remappable RPA2. |
| 31 | OSC2/CLKO/RPA3/RA3 | bidirectional | Oscillator crystal output connecting to crystal or resonator, optionally CLKO in RC and EC modes, shared with PORTA RA3 and remappable RPA3. |
| 32 | TDO/RPA8/PMA8/RA8 | bidirectional | PORTA I/O RA8 with JTAG test data output TDO, remappable RPA8 and PMP address bit PMA8. |
| 33 | SOSCI/RPB4/RB4 | bidirectional | 32.768 kHz secondary oscillator crystal input, shared with PORTB RB4 and remappable RPB4. |
| 34 | SOSCO/RPA4/T1CK/CTED9/RA4 | bidirectional | 32.768 kHz secondary oscillator crystal output, shared with PORTA RA4, remappable RPA4, Timer1 clock T1CK and CTED9. |
| 35 | TDI/RPA9/PMA9/RA9 | bidirectional | PORTA I/O RA9 with JTAG test data input TDI, remappable RPA9 and PMP address bit PMA9. |
| 36 | RPC3/RC3 | bidirectional | PORTC I/O RC3 with remappable RPC3. |
| 37 | RPC4/PMA4/RC4 | bidirectional | PORTC I/O RC4 with remappable RPC4 and PMP address bit PMA4. |
| 38 | RPC5/PMA3/RC5 | bidirectional | PORTC I/O RC5 with remappable RPC5 and PMP address bit PMA3. |
| 39 | VSS | power_in | Ground reference for logic and I/O pins; must be connected at all times. |
| 40 | VDD | power_in | Positive supply for peripheral logic and I/O pins. |
| 41 | PGED3/RPB5/PMD7/RB5 | bidirectional | PORTB I/O RB5 with ICSP data channel 3 PGED3, remappable RPB5 and PMP data bit PMD7. |
| 42 | PGEC3/RPB6/PMD6/RB6 | bidirectional | PORTB I/O RB6 with ICSP clock channel 3 PGEC3, remappable RPB6 and PMP data bit PMD6. |
| 43 | RPB7/CTED3/PMD5/INT0/RB7 | bidirectional | PORTB I/O RB7 with remappable RPB7, CTED3, PMP data bit PMD5 and external interrupt INT0. |
| 44 | RPB8/SCL1/CTED10/PMD4/RB8 | bidirectional | PORTB I/O RB8 with remappable RPB8, I2C1 clock SCL1, CTED10 and PMP data bit PMD4. |
| 45 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-44-EP(8x8) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 45 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating supply voltage | VDD | 2.3 | 3.6 | V | Operating conditions, front page | 1 | |
| Operating temperature (industrial, 50 MHz) | TA | -40 | 85 | °C | DC to 50 MHz | 1 | |
| CPU frequency (industrial) | fSYSCLK | 0 | 50 | MHz | 2.3V to 3.6V, -40°C to +85°C | 1 | |
| Port Output Rise Time | TIOR | 5 | 15 | ns | VDD < 2.5V | 276 | |
| Port Output Rise Time | TIOR | 5 | 10 | ns | VDD > 2.5V | 276 | |
| Port Output Fall Time | TIOF | 5 | 15 | ns | VDD < 2.5V | 276 | |
| Port Output Fall Time | TIOF | 5 | 10 | ns | VDD > 2.5V | 276 | |
| INTx Pin High or Low Time | TINP | 10 | ns | 276 | |||
| CNx High or Low Time (input) | TRBP | 2 | TSYSCLK | 276 | |||
| Dynamic current | 0.5 | mA/MHz | typical, front page | 1 | |||
| IPD current | IPD | 44 | μA | typical, front page | 1 |
CAD (KiCad official)
- Symbol:
PIC32MX150F128D-I - Footprint:
Package_DFN_QFN:QFN-44-1EP_8x8mm_P0.65mm_EP6.45x6.45mm - 3D model: QFN-44-EP(8x8) (KiCad packages3D, STEP)
- 3D model files:
pic32mx150f128d-i-etched.step/pic32mx150f128d-i-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);pic32mx150f128d-i.step/pic32mx150f128d-i.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (350 pp, sha256
6f75ee8fe58045ff, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).