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CDCE6214TWRGETQ1

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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timingcdce6214twrgetq1factory-2.0.0extractor-text

Verified CDCE6214TWRGETQ1

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 25 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCE6214TWRGETQ1 · VQFN-24-EP(4x4) · 25 pins
  • ✓copper: 25 copper pads, none touching another net
  • ✓datasheet: all 25 pin names found in the 53-page datasheet
  • ✓distributor: lcsc C1235975, digikey 296-CDCE6214TWRGETQ1TR-ND, mouser 595-CDCE6214TWRGETQ1
  • ✓family: QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-e8lomyw3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 25 pins = 25 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 25 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdce6214twrgetq1.kicad_sym✓ cdce6214twrgetq1.kicad_mod✓ cdce6214twrgetq1.step
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Contents

README

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CDCE6214TWRGETQ1

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-24-EP(4x4)

CDCE6214TWRGETQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SECREF_P input Secondary reference clock positive input; accepts a differential or single-ended input or XTAL, with AC-coupling capacitors required and internal differential biasing disabled in single-ended and XTAL modes.
2 SECREF_N input Secondary reference clock negative input; accepts a differential or single-ended input or XTAL, with AC-coupling capacitors required and internal differential biasing disabled in single-ended and XTAL modes.
3 VDD_REF power_in 1.8 V/2.5 V/3.3 V power supply for the reference input and digital blocks; the datasheet gives a 1.71 V to 3.465 V recommended range.
4 REFSEL input Manual 3-level reference input selection pin with weak pullup/pulldown (RPU = 50 kΩ, RPD = 50 kΩ).
5 PRIREF_P input Primary reference clock positive input; accepts a differential or single-ended input with AC-coupling capacitors required, and the non-driven input must be pulled down to ground for LVCMOS.
6 PRIREF_N input Primary reference clock negative input; accepts a differential or single-ended input with AC-coupling capacitors required, and the non-driven input must be pulled down to ground for LVCMOS.
7 OUT0 output LVCMOS output 0 with configurable slew rate; the reference input can be bypassed into this output and it is excluded from the global output enable.
8 PDN input Device power-down/reset input (active low) or SYNCN, with a weak 50 kΩ pullup resistor.
9 OUT4_N output Output pair 4 negative; programmable as LVDS-like/LP-HCSL or as 2x LVCMOS outputs.
10 OUT4_P output Output pair 4 positive; programmable as LVDS-like/LP-HCSL or as 2x LVCMOS outputs.
11 GPIO4 bidirectional STATUS output or GPIO4 input with a weak 50 kΩ pullup enabled when configured as input and disabled in output mode.
12 SCL/GPIO3 input I2C serial clock or GPIO3 input; requires an external pullup resistor to VDD_REF in I2C mode and is a fail-safe input.
13 OUT3_N output Output pair 3 negative; programmable LVDS-like or LP-HCSL output.
14 OUT3_P output Output pair 3 positive; programmable LVDS-like or LP-HCSL output.
15 VDDO_34 power_in 1.8 V/2.5 V/3.3 V power supply for the OUT0, OUT3 and OUT4 channels; the datasheet gives a 1.71 V to 3.465 V recommended range.
16 VDDO_12 power_in 1.8 V/2.5 V/3.3 V power supply for the OUT1 and OUT2 channels; the datasheet gives a 1.71 V to 3.465 V recommended range.
17 OUT2_N output Output pair 2 negative; programmable LVDS-like or LP-HCSL output.
18 OUT2_P output Output pair 2 positive; programmable LVDS-like or LP-HCSL output.
19 SDA/GPIO2 bidirectional I2C serial data (open-drain) or GPIO2 input; requires an external pullup resistor to VDD_REF in I2C mode and is a fail-safe input.
20 GPIO1 bidirectional STATUS output or GPIO1 input with a weak 50 kΩ pullup enabled when configured as input and disabled in output mode.
21 OUT1_N output Output pair 1 negative; programmable as LVDS-like/LP-HCSL or as 2x LVCMOS outputs.
22 OUT1_P output Output pair 1 positive; programmable as LVDS-like/LP-HCSL or as 2x LVCMOS outputs.
23 HW_SW_CTRL input Manual 3-level EEPROM page select pin with weak pullup/pulldown (RPU = 50 kΩ, RPD = 50 kΩ), sampled after power-up.
24 VDD_VCO power_in 1.8 V/2.5 V/3.3 V power supply for the PLL/VCO; the datasheet gives a 1.71 V to 3.465 V recommended range.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x4)
Category Clock and Timing
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD_REF, VDD_VCO, VDDO_12, VDDO_34) -0.3 3.63 V 5
Junction Temperature TJ 125 °C 5
Storage temperature Tstg -65 150 °C 5
Core supply voltage VDD_VCO 1.71 3.465 V 5
Output supply voltage VDDO_12 1.71 3.465 V 5
Reference supply voltage VDD_REF 1.71 3.465 V 5
Ambient temperature TA -40 105 °C 5
Junction temperature TJ -40 125 °C 5
Continuous lock over temperature TLOCK 145 °C without VCO calibration 5
Maximum supply voltage ramp time tRAMP 0.1 30 ms 5
Reference frequency fIN_Ref 10 200 MHz 6
Input duty cycle IDC 40 60 % 6
Input leakage current IIN_LEAKAGE -100 100 µA 6
Differential input voltage swing, peak-to-peak VIN_DIFF 0.4 1.6 V VDD_REF = 2.5 V/3.3 V 6
Differential input voltage swing, peak-to-peak VIN_DIFF 0.4 1 V VDD_REF = 1.8 V 6
Crystal frequency fIN_Xtal 10 50 MHz Fundamental mode 6
Crystal tolerated drive power PXTAL 200 µW A supported crystal 6
On-Chip load capacitance CXIN_LOAD 3 9.1 pF Programmable in typ. 200 fF steps 6
Input high level current IIH -5 5 µA VIH = VDD_REF, GPIO[1:4], PDN 7
Input low level current IIL -5 5 µA VIL = GND, GPIO[2:3] 7
Input low level current IIL -100 100 µA VIL = GND, GPIO[1], GPIO[4], PDN 7
Pullup Resistance RPU 30 55 80 kΩ Pins PDN, GPIO[1], GPIO[4] 7
Input high level current (triple level) IIH 20 50 100 µA VIH = VDD_REF 7
Input low level current (triple level) IIL -100 -50 -20 µA VIL = GND 7
Phase Detector Frequency fPFD 1 100 MHz Integer and Fractional PLL mode 7
Voltage Controlled Oscillator Frequency fVCO 2335 2625 MHz 7
Configurable closed-loop PLL Bandwidth fBW 100 1600 kHz REF = 25 MHz 7
RMS Phase Jitter (int-PLL) tRJ_CL 350 600 fs RMS jitter with spurs from 12 kHz to 20 MHz, Input Crystal = 25 MHz, Differential OUTx > 100 MHz, int-PLL 8
RMS Phase Jitter (frac-PLL) tRJ_CL 1600 2100 fs RMS jitter with spurs from 12 kHz to 20 MHz, Input Crystal = 25 MHz, Differential OUTx > 100 MHz, frac-PLL 8
RMS Phase Jitter (PCIe) tRJ_CL, PCIE 475 1000 fs PCIe Gen 3 Filter applied, XIN = Crystal 25 MHz, OUTx = 100 MHz, frac-N PLL with and without SSC, LP-HCSL or LVDS output 8
Input-to-output delay variation in ZDB mode tPROP-VARIATION -400 400 ps ZDB mode, LVCMOS input = LVCMOS output = 25 MHz, PLL BW = 300 kHz to 900 kHz across temperature 8
SSC modulation rate fSSC-RATE 30 31.5 33 kHz OUTx = 100 MHz 8
Down spread minimum/maximum deviation tSSC_FREQ_DEVIATION -0.5 0 % OUTx = 100 MHz. FPFD = 25 MHz, 50 MHz, 100 MHz 9
Center spread minimum/maximum deviation tSSC_FREQ_DEVIATION -0.5 0.5 % OUTx = 100 MHz. FPFD = 25 MHz, 50 MHz, 100 MHz 9
Output frequency fO_LVCMOS 0.024 200 MHz 2 pF to GND, normal mode 9
Output rise/fall time TRISE-FALL 300 500 700 ps 20/80%, CL= 5 pF, normal mode 9
Output impedance RON_LVCMOS 45 60 75 Ω Normal mode 9
Output impedance RON_LVCMOS 50 65 85 Ω Slow mode 9
Output duty cycle (LVCMOS) ODC 45 55 % Not in PLL bypass mode 9
Output frequency (LP-HCSL) fO_HCSL 0.024 328.125 MHz 9
Output high voltage (LP-HCSL) VOH 660 850 mV 9
Output low voltage (LP-HCSL) VOL -150 150 mV 9
Differential Output Impedance ZDIFF 90 100 110 Ω 9
Absolute crossing point VCROSS 250 550 mV 12-in, 100 Ω ±10% diff. trace with 2 pF±5%/pin in FR4. 9
Slew rate for rising and falling edge differential dV/dt 1 4 V/ns at VCROSS +/-150 mV, fO_HCSL=100 MHz 9
Output ringback voltage Vrb -100 100 mV Measured on differential output at 100 MHz and specifies minimum voltage from zero crossing 9
Output common mode VCM 1.025 1.2 1.375 V VDDO_X = 2.5 V, 3.3 V 10
Output common mode VCM 0.85 0.95 1.05 V VDDO_X = 1.8 V 10
Differential output voltage VOD 0.25 0.3 0.45 V VDDO_X = 1.8 V (Fout < 200 MHz), 2.5 V, 3.3 V 10
Differential output voltage VOD 0.22 0.3 0.45 V VDDO_X = 1.8 V & Fout > 200 MHz 10
Output frequency (LVDS) fO_PRG_AC 0.024 328.125 MHz 10
Output rise/fall times LVDS (20% to 80%) tRF 450 650 900 ps 10
Output duty cycle (LVDS) ODC 45 55 % Not in PLL bypass mode 10
Typical current, 4 x 100 MHz LVDS IDD_TYP 50 70 mA 4 x 100 MHz LVDS case using crystal input and doubler, SSC off 12
Typical current, 4 x 100 MHz LP-HCSL IDD_TYP 65 90 mA 4 x 100 MHz LP-HCSL case using crystal input and doubler, SSC off 12
Junction-to-ambient thermal resistance RθJA 32.5 °C/W RGE (VQFN) 24 pins 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 2 °C/W RGE (VQFN) 24 pins 5

CAD (KiCad official)

  • Symbol: CDCE6214TWRGETQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: cdce6214twrgetq1-etched.step / cdce6214twrgetq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce6214twrgetq1.step / cdce6214twrgetq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (53 pp, sha256 91c3c761fb571a33, retrieved 2026-11-02, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF