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NL17SZ08XV5T2G

Public Made by Adom

by adom

onsemi Logic Gates, SOT-553-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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NL17SZ08XV5T2G

onsemi · Logic Gates · SOT-553-5

NL17SZ08XV5T2G from onsemi, in a SOT-553-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN B input Data input B of the 2-input AND gate; the DC input voltage range is 0 to 5.5 V and the inputs are overvoltage tolerant.
2 IN A input Data input A of the 2-input AND gate; the DC input voltage range is 0 to 5.5 V and the inputs are overvoltage tolerant.
3 GND power_in Ground reference pin for the device.
4 OUT Y output AND gate output Y (Y = A·B); for this package the DC output voltage is limited to 0 to 5.5 V and the DC output sink current to ±50 mA.
5 VCC power_in Positive supply pin; recommended operating supply range is 1.65 V to 5.5 V, with a DC supply voltage absolute maximum of 7.0 V.

Key specifications

Parameter Value
Manufacturer onsemi
Package SOT-553-5
Category Logic
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage VCC -0.5 7 V 2
DC Input Voltage VIN -0.5 7 V 2
DC Output Voltage (SOT-553 package) VOUT -0.5 7 V SOT-353/SC70-5/SC-88A/SOT-553 Packages 2
DC Input Diode Current IIK -50 mA 2
DC Output Diode Current (SOT-553 package) IOK -50 mA VOUT < GND 2
DC Output Sink Current IOUT -50 50 mA 2
DC Supply Current per Supply Pin ICC -100 100 mA 2
Storage Temperature Range TSTG -65 150 °C 2
Lead Temperature TL 260 °C 1 mm from case for 10 seconds 2
Junction Temperature Under Bias TJ 150 °C 2
Thermal Resistance (SOT-553) JA 496 °C/W SOT-553 (Note 1) 2
Power Dissipation in Still Air at 85°C (SOT-553) PD 135 mW SOT-553, still air at 85°C 2
ESD Human Body Model ESD 2000 V Human Body Model (Note 2) 2
ESD Machine Model ESD 200 V Machine Model (Note 3) 2
Latchup Performance ILATCHUP -100 100 mA Above VCC and below GND at 125°C (Note 5) 2
DC Supply Voltage VCC 1.65 5.5 V 3
DC Input Voltage VIN 0 5.5 V 3
DC Output Voltage (SOT-553 package) VOUT 0 5.5 V SOT-353/SC70-5/SC-88A/SOT-553 Packages 3
Operating Temperature Range TA -55 125 °C 3
Input Rise and Fall Time tr, tf 0 100 ns/V VCC = 3.0 V ±0.3 V 3
Input Rise and Fall Time tr, tf 0 20 ns/V VCC = 5.0 V ±0.5 V 3
High-Level Output Voltage VOH 1.29 1.52 V VIN = VIL or VIH; IOH = −3 mA; VCC = 1.65 V 3
High-Level Output Voltage VOH 1.9 2.1 V VIN = VIL or VIH; IOH = −8 mA; VCC = 2.3 V 3
High-Level Output Voltage VOH 2.2 2.4 V VIN = VIL or VIH; IOH = −12 mA; VCC = 2.7 V 3
High-Level Output Voltage VOH 2.4 2.7 V VIN = VIL or VIH; IOH = −16 mA; VCC = 3.0 V 3
High-Level Output Voltage VOH 2.3 2.5 V VIN = VIL or VIH; IOH = −24 mA; VCC = 3.0 V 3
High-Level Output Voltage VOH 3.8 4 V VIN = VIL or VIH; IOH = −32 mA; VCC = 4.5 V 3
Low-Level Output Voltage VOL 0.08 0.1 V VIN = VIH or VOH; IOL = 100 µA; VCC = 1.65 to 5.5 V 3
Low-Level Output Voltage VOL 0.2 0.24 V VIN = VIH or VOH; IOL = 3 mA; VCC = 1.65 V 3
Low-Level Output Voltage VOL 0.22 0.3 V VIN = VIH or VOH; IOL = 8 mA; VCC = 2.3 V 3
Low-Level Output Voltage VOL 0.28 0.4 V VIN = VIH or VOH; IOL = 12 mA; VCC = 2.7 V 3
Low-Level Output Voltage VOL 0.38 0.4 V VIN = VIH or VOH; IOL = 16 mA; VCC = 3.0 V 3
Low-Level Output Voltage VOL 0.42 0.55 V VIN = VIH or VOH; IOL = 24 mA; VCC = 3.0 V 3
Low-Level Output Voltage VOL 0.55 V VIN = VIH or VOH; IOL = 32 mA; VCC = 4.5 V 3
Input Leakage Current IIN -1 1 µA VIN = 5.5 V or GND; VCC = 0 to 5.5 V 3
Quiescent Supply Current ICC 10 µA VIN = 5.5 V or GND; VCC = 5.5 V 3
Power Off Leakage Current (SOT-553 package) IOFF 10 µA VIN = 5.5 V or VOUT = 5.5 V; VCC = 0 V 3
Propagation Delay (TA = 25C) tPLH, tPHL 2 6.3 12 ns RL = 1 M, CL = 15 pF; VCC = 1.65 V 4
Propagation Delay (TA = 25C) tPLH, tPHL 2 6.2 10 ns RL = 1 M, CL = 15 pF; VCC = 1.8 V 4
Propagation Delay (TA = 25C) tPLH, tPHL 0.8 3.4 7 ns RL = 1 M, CL = 15 pF; VCC = 2.5 ± 0.2 V 4
Propagation Delay (TA = 25C) tPLH, tPHL 0.5 2.6 4.7 ns RL = 1 M, CL = 15 pF; VCC = 3.3 ± 0.3 V 4
Propagation Delay (TA = 25C) tPLH, tPHL 1.5 3.3 5.2 ns RL = 500, CL = 50 pF; VCC not printed on row 4
Propagation Delay (TA = 25C) tPLH, tPHL 0.5 2.2 4.1 ns RL = 1 M, CL = 15 pF; VCC = 5.0 ± 0.5 V 4
Propagation Delay (TA = 25C) tPLH, tPHL 0.8 2.7 4.5 ns RL = 500, CL = 50 pF; VCC = 5.0 ± 0.5 V 4
Propagation Delay (−55C to 125C) tPLH, tPHL 2 12.7 ns RL = 1 M, CL = 15 pF; VCC = 1.65 V 4
Propagation Delay (−55C to 125C) tPLH, tPHL 2 10.5 ns RL = 1 M, CL = 15 pF; VCC = 1.8 V 4
Propagation Delay (−55C to 125C) tPLH, tPHL 0.8 7.5 ns RL = 1 M, CL = 15 pF; VCC = 2.5 ± 0.2 V 4
Propagation Delay (−55C to 125C) tPLH, tPHL 0.5 5 ns RL = 1 M, CL = 15 pF; VCC = 3.3 ± 0.3 V 4
Propagation Delay (−55C to 125C) tPLH, tPHL 1.5 5.5 ns RL = 500, CL = 50 pF; VCC not printed on row 4
Propagation Delay (−55C to 125C) tPLH, tPHL 0.5 4.4 ns RL = 1 M, CL = 15 pF; VCC = 5.0 ± 0.5 V 4
Propagation Delay (−55C to 125C) tPLH, tPHL 0.8 4.8 ns RL = 500, CL = 50 pF; VCC = 5.0 ± 0.5 V 4
Input Capacitance CIN 4 pF VCC = 5.5 V, VI = 0 V or VCC 4
Power Dissipation Capacitance CPD 25 pF 10 MHz, VCC = 3.3 V, VI = 0 V or VCC 4
Power Dissipation Capacitance CPD 30 pF 10 MHz, VCC = 5.5 V, VI = 0 V or VCC 4

CAD (KiCad official)

  • Symbol: NL17SZ08XV5T2G
  • Footprint: Package_TO_SOT_SMD:SOT-553
  • 3D model: SOT-553-5 (KiCad packages3D, STEP)
  • 3D model files: nl17sz08xv5t2g-etched.step / nl17sz08xv5t2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); nl17sz08xv5t2g.step / nl17sz08xv5t2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (7 pp, sha256 84ecb32b1632703a, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF