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TPS74501PBQWDRVRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, WSON-6-EP(2x2). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownTPS74501PBQWDRVRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · WSON-6-EP(2x2)
TPS74501PBQWDRVRQ1 from Texas Instruments, in a WSON-6-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output voltage pin; requires 0.47µF to 220µF ceramic output capacitor placed close to device for stability. |
| 2 | FB | input | Feedback input pin for control loop to set adjustable output voltage from 0.55V to 5.5V; requires external resistor divider with series resistance ≤VOUT/(IFB×100). |
| 3 | GND | power_in | Ground reference pin; thermal pad electrically connected to GND and should be soldered to ground plane for improved thermal performance. |
| 4 | EN | input | Enable input pin; drive EN≥VEN(HI)=1.0V to enable regulator, EN≤VEN(LO)=0.3V for shutdown mode; internal pull-down resistance of 95Ω. |
| 5 | PG | tri_state | Open-drain power-good output with 5ms delay; asserts low when VOUT falls below 86-90% nominal; external pull-up resistor required. |
| 6 | IN | power_in | Supply voltage input pin accepting 1.5V to 6.0V; use 1µF or larger ceramic input capacitor placed close to pin to minimize impedance. |
| 7 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-6-EP(2x2) |
| Category | Power Management (PMIC) |
| Pins | 7 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output accuracy (TJ = 25°C) | -0.85 | 0.85 | % | TJ = 25°C | 5 | ||
| Output accuracy (-40°C to 85°C) | -1 | 1 | % | -40°C ≤ TJ ≤ 85°C | 5 | ||
| Output accuracy (-40°C to 150°C) | -1.5 | 1.5 | % | -40°C ≤ TJ ≤ 150°C | 5 | ||
| Output current limit | ICL | 515 | 720 | 865 | mA | VOUT(NOM) < 1.0 V, VOUT = VOUT(NOM) - 0.2 V, VIN = 2.0 V; VOUT(NOM) ≥ 1.0 V, VOUT = VOUT(NOM) x 0.85, VIN = VOUT(NOM) + 1.0 V | 5 |
| Short-circuit current limit | ISC | 200 | 350 | 400 | mA | VOUT = 0 V; VOUT(NOM) < 1.0 V, VIN = 2.0 V; VOUT(NOM) ≥ 1.0 V, VIN = VOUT(NOM) + 1.0 V | 5 |
| Undervoltage lockout (VIN falling) | VUVLO | 1.17 | 1.3 | 1.42 | V | VIN falling | 5 |
| Undervoltage lockout (VIN rising) | VUVLO | 1.21 | 1.34 | 1.47 | V | VIN rising | 5 |
| Startup time | tSTR | 200 | 500 | 650 | µs | From EN low-to-high transition to VOUT = VOUT(NOM) x 0.95 | 6 |
| PG high threshold | PGHTH | 89 | 92 | 96 | %VOUT | VOUT increasing | 6 |
| PG low threshold | PGLTH | 86 | 90 | 93 | %VOUT | VOUT decreasing | 6 |
| PG delay time rising ('B' version) | tPGDH | 4.5 | 5 | 5.5 | ms | 'B' version; time from 92% VOUT to 20% of PG; output overdrive = 10% | 6 |
| PG delay time falling | tPGDL | 1.5 | 7 | 10 | µs | Time from 90% VOUT to 80% of PG; output overdrive = 10% | 6 |
| PG pin low-level output voltage | VOL(PG) | 300 | mV | VIN ≥ 1.5V, ISINK = 1.0 mA | 6 | ||
| PG pin leakage current | Ilkg(PG) | 7 | 50 | nA | VOUT > PGHTH, VPG = 6.0 V | 6 | |
| Shutdown current | ISHDN | 0.1 | 1 | µA | VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V, -40°C ≤ TJ ≤ 125°C | 5 | |
| Shutdown current | ISHDN | 0.1 | 1.55 | µA | VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V, -40°C ≤ TJ ≤ 150°C | 5 | |
| Ground current | IGND | 25 | 32 | µA | IOUT = 0 mA, TJ = 25°C | 5 | |
| Ground current | IGND | 25 | 36 | µA | IOUT = 0 mA, -40°C ≤ TJ ≤ 150°C | 5 | |
| Feedback pin current (adjustable only) | IFB | 0.01 | 0.1 | µA | Adjustable only | 5 | |
| Line regulation | 2 | 7.5 | mV | VOUT(NOM) + 0.5 V ≤ VIN ≤ 6.0 V | 5 | ||
| Dropout voltage (0.65 V ≤ VOUT < 0.8 V) | VDO | 720 | 910 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 0.65 V ≤ VOUT < 0.8 V | 5 | |
| Dropout voltage (0.8 V ≤ VOUT < 1.0 V) | VDO | 585 | 780 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 0.8 V ≤ VOUT < 1.0 V | 5 | |
| Dropout voltage (1.0 V ≤ VOUT < 1.2 V) | VDO | 420 | 600 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 1.0 V ≤ VOUT < 1.2 V | 5 | |
| Dropout voltage (1.2 V ≤ VOUT < 1.5 V) | VDO | 285 | 430 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 1.2 V ≤ VOUT < 1.5 V | 5 | |
| Dropout voltage (1.5 V ≤ VOUT < 1.8 V) | VDO | 180 | 265 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 1.5 V ≤ VOUT < 1.8 V | 5 | |
| Dropout voltage (1.8 V ≤ VOUT < 2.5 V) | VDO | 140 | 215 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 1.8 V ≤ VOUT < 2.5 V | 5 | |
| Dropout voltage (2.5 V ≤ VOUT < 3.3 V) | VDO | 105 | 170 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 2.5 V ≤ VOUT < 3.3 V | 5 | |
| Dropout voltage (3.3 V ≤ VOUT ≤ 5.5 V) | VDO | 95 | 160 | mV | IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM); 3.3 V ≤ VOUT ≤ 5.5 V | 5 | |
| EN pin high voltage (enabled) | VEN(HI) | 1 | V | 6 | |||
| EN pin low voltage (disabled) | VEN(LO) | 0.3 | V | 6 | |||
| Feedback voltage (adjustable only) | VFB | 0.55 | V | Adjustable only | 5 | ||
| Thermal shutdown (shutdown) | TSD | 170 | °C | Shutdown, temperature increasing | 6 | ||
| Thermal shutdown (reset) | TSD | 155 | °C | Reset, temperature decreasing | 6 | ||
| Supply voltage | VIN | -0.3 | 6.5 | V | 4 | ||
| Enable voltage | VEN | -0.3 | 6.5 | V | 4 | ||
| Feedback voltage | VFB | -0.3 | 2 | V | 4 | ||
| Power-good voltage | VPG | -0.3 | 6.5 | V | 4 | ||
| Output voltage | VOUT | -0.3 | V | Printed as VIN + 0.3 V (footnote: VIN + 0.3 V or 6.0 V, whichever is smaller) | 4 | ||
| Power-good current | IPG | -10 | 10 | mA | 4 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Input voltage | VIN | 1.5 | 6 | V | 4 | ||
| Output voltage (adjustable only) | VOUT | 0.55 | 5.5 | V | Adjustable only | 4 | |
| Output current | IOUT | 0 | 500 | mA | 4 | ||
| Output capacitor | COUT | 1 | 220 | µF | 4 | ||
| Enable voltage | VEN | 0 | 6 | V | 4 | ||
| PG voltage | VPG | 0 | 6 | V | 4 | ||
| Junction operating temperature | TJ | -40 | 150 | °C | 4 | ||
| Junction-to-ambient thermal resistance (DRV WSON) | RθJA | 80.3 | °C/W | DRV (6-pin WSON) package | 5 | ||
| Junction-to-case (top) thermal resistance (DRV WSON) | RθJC(top) | 98.7 | °C/W | DRV (6-pin WSON) package | 5 | ||
| Junction-to-board thermal resistance (DRV WSON) | RθJB | 44.8 | °C/W | DRV (6-pin WSON) package | 5 | ||
| Junction-to-case (bottom) thermal resistance (DRV WSON) | RθJC(bot) | 20.8 | °C/W | DRV (6-pin WSON) package | 5 |
CAD (KiCad official)
- Symbol:
TPS74501PBQWDRVRQ1 - Footprint:
Package_SON:WSON-6-1EP_2x2mm_P0.65mm_EP1x1.6mm - 3D model: WSON-6-EP(2x2) (KiCad packages3D, STEP)
- 3D model files:
tps74501pbqwdrvrq1-etched.step/tps74501pbqwdrvrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps74501pbqwdrvrq1.step/tps74501pbqwdrvrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
434ed7c32560a28e, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).