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74AHC595PW

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Nexperia Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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74AHC595PW

Nexperia · Shifting Register · TSSOP-16

74AHC595PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output bit 1. 3-state output; high-impedance when OE is HIGH. Drives ±8 mA at VCC = 4.5 V (VOH ≥ 3.94 V, VOL ≤ 0.36 V typical).
2 Q2 tri_state Parallel data output bit 2. 3-state output; high-impedance when OE is HIGH.
3 Q3 tri_state Parallel data output bit 3. 3-state output; high-impedance when OE is HIGH.
4 Q4 tri_state Parallel data output bit 4. 3-state output; high-impedance when OE is HIGH.
5 Q5 tri_state Parallel data output bit 5. 3-state output; high-impedance when OE is HIGH.
6 Q6 tri_state Parallel data output bit 6. 3-state output; high-impedance when OE is HIGH.
7 Q7 tri_state Parallel data output bit 7. 3-state output; high-impedance when OE is HIGH.
8 GND power_in Ground reference (0 V). Max IGND = -75 mA.
9 Q7S output Serial data output from the last shift register stage (Q7 of the shift register, not the storage register). Used to cascade multiple 595s. Not 3-stated by OE.
10 MR input Master reset, active LOW. A LOW asynchronously clears the shift register only (storage register/parallel outputs unaffected until STCP is clocked). Schmitt-trigger input, overvoltage tolerant to 5.5 V.
11 SHCP input Shift register clock input. Data on DS is shifted on the LOW-to-HIGH transition. Max frequency 130 MHz (VCC 4.5-5.5 V). Schmitt-trigger input.
12 STCP input Storage register clock input. A LOW-to-HIGH transition transfers the shift register contents to the 8-bit storage register and to the parallel outputs. Schmitt-trigger input.
13 OE input Output enable, active LOW. A HIGH forces Q0-Q7 into the high-impedance OFF-state; does not affect the shift or storage register contents. Schmitt-trigger input.
14 DS input Serial data input to the shift register. Sampled on the LOW-to-HIGH edge of SHCP. Schmitt-trigger input, overvoltage tolerant to 5.5 V.
15 Q0 tri_state Parallel data output bit 0. 3-state output; high-impedance when OE is HIGH.
16 VCC power_in Supply voltage. 2.0 V to 5.5 V (74AHC595); 4.5 V to 5.5 V (74AHCT595). Absolute max 7.0 V. Recommend local 0.1 µF decoupling to GND.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74AHC595PW
  • 74AHC595PWD
  • 74AHC595PWBQ

CAD (KiCad official)

  • Symbol: 74AHC595PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74ahc595pw-etched.step / 74ahc595pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74ahc595pw.step / 74ahc595pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 67d6cf86d0a75a0a, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF