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CY8C4147AZI-S465

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Infineon Technologies Microcontrollers (MCU/MPU/SOC), TQFP-64(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CY8C4147AZI-S465

Infineon Technologies · Microcontrollers (MCU/MPU/SOC) · TQFP-64(14x14)

CY8C4147AZI-S465 from Infineon Technologies, in a TQFP-64(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional Port 1 GPIO bit 7, also usable as ctb0_oa1+, sar_ext_vref0/1 and SmartIo[2].io[7]; any GPIO can be configured as CapSense, analog or digital with programmable drive mode and strength, max 25 mA per GPIO.
2 P2.0 bidirectional Port 2 GPIO bit 0, also sarmux[0] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
3 P2.1 bidirectional Port 2 GPIO bit 1, also sarmux[1] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
4 P2.2 bidirectional Port 2 GPIO bit 2, also sarmux[2] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
5 P2.3 bidirectional Port 2 GPIO bit 3, also sarmux[3] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
6 P2.4 bidirectional Port 2 GPIO bit 4, also sarmux[4] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
7 P2.5 bidirectional Port 2 GPIO bit 5, also sarmux[5] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
8 P2.6 bidirectional Port 2 GPIO bit 6, also sarmux[6] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
9 P2.7 bidirectional Port 2 GPIO bit 7, also sarmux[7] analog input; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
10 VSSD power_in Ground pin for the digital section, to be connected to system ground.
11 NC unconnected No connect pin.
12 P6.0 bidirectional Port 6 GPIO bit 0, also CAN can_tx_enb_n and SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
13 P6.1 bidirectional Port 6 GPIO bit 1, also CAN can_rx and SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
14 P6.2 bidirectional Port 6 GPIO bit 2, also CAN can_tx and SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
15 P6.4 bidirectional Port 6 GPIO bit 4, also TCPWM and SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
16 P6.5 bidirectional Port 6 GPIO bit 5, also TCPWM and SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
17 VSSD power_in Ground pin for the digital section, to be connected to system ground.
18 P3.0 bidirectional Port 3 GPIO bit 0, also SmartIO and SCB1 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
19 P3.1 bidirectional Port 3 GPIO bit 1, also SmartIO and SCB1 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
20 P3.2 bidirectional Port 3 GPIO bit 2, also the cpuss.swd_data Serial Wire Debug data function and SCB1 alternate functions; max 25 mA per GPIO.
21 P3.3 bidirectional Port 3 GPIO bit 3, also the cpuss.swd_clk Serial Wire Debug clock function and SCB1 alternate functions; max 25 mA per GPIO.
22 P3.4 bidirectional Port 3 GPIO bit 4, also SmartIO, TCPWM and SCB1 alternate functions; max 25 mA per GPIO.
23 P3.5 bidirectional Port 3 GPIO bit 5, also SmartIO, TCPWM and SCB1 alternate functions; max 25 mA per GPIO.
24 P3.6 bidirectional Port 3 GPIO bit 6, also SmartIO, TCPWM and SCB1/SCB4 alternate functions; max 25 mA per GPIO.
25 P3.7 bidirectional Port 3 GPIO bit 7, also SmartIO, LP comparator comp[1] and SCB2 alternate functions; max 25 mA per GPIO.
26 VDDD power_in Power supply for the digital section, 1.8 V to 5.5 V in internally regulated mode or 1.71 V to 1.89 V with the regulator bypassed.
27 P4.0 bidirectional Port 4 GPIO bit 0, also CSD vref_ext, CAN rx and SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
28 P4.1 bidirectional Port 4 GPIO bit 1, also CSD cshield, CAN tx and SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
29 P4.2 bidirectional Port 4 GPIO bit 2, also CSD cmod (modulator capacitor), CAN tx enable and SCB0 alternate functions; max 25 mA per GPIO.
30 P4.3 bidirectional Port 4 GPIO bit 3, also CSD csh_tank and SCB0 alternate functions; max 25 mA per GPIO.
31 P4.4 bidirectional Port 4 GPIO bit 4, also SCB4 and SCB0 alternate functions; max 25 mA per GPIO.
32 P4.5 bidirectional Port 4 GPIO bit 5, also SCB4 and SCB0 alternate functions; max 25 mA per GPIO.
33 P4.6 bidirectional Port 4 GPIO bit 6, also SCB4 and SCB0 alternate functions; max 25 mA per GPIO.
34 P4.7 bidirectional Port 4 GPIO bit 7, also SCB4 alternate functions; max 25 mA per GPIO.
35 P5.6 bidirectional Port 5 GPIO bit 6, also TCPWM and SCB4/SCB2 alternate functions; max 25 mA per GPIO.
36 P5.7 bidirectional Port 5 GPIO bit 7, also TCPWM and SCB4 alternate functions; max 25 mA per GPIO.
37 P7.0 bidirectional Port 7 GPIO bit 0, also TCPWM and SCB3 alternate functions; max 25 mA per GPIO.
38 P7.1 bidirectional Port 7 GPIO bit 1, also TCPWM and SCB3 alternate functions; max 25 mA per GPIO.
39 P0.0 bidirectional Port 0 GPIO bit 0, also LP comparator lpcomp.in_p[0] and SCB2/SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
40 P0.1 bidirectional Port 0 GPIO bit 1, also LP comparator lpcomp.in_n[0] and SCB2/SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
41 P0.2 bidirectional Port 0 GPIO bit 2, also LP comparator lpcomp.in_p[1] and SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
42 P0.3 bidirectional Port 0 GPIO bit 3, also LP comparator lpcomp.in_n[1] and SCB2 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
43 P0.4 bidirectional Port 0 GPIO bit 4, also the 32-kHz watch crystal input wco_in and SCB1/SCB2 alternate functions; max 25 mA per GPIO.
44 P0.5 bidirectional Port 0 GPIO bit 5, also the 32-kHz watch crystal output wco_out and SCB1/SCB2 alternate functions; max 25 mA per GPIO.
45 P0.6 bidirectional Port 0 GPIO bit 6, also the external crystal oscillator input eco_in and SCB1/SCB2 alternate functions; max 25 mA per GPIO.
46 P0.7 bidirectional Port 0 GPIO bit 7, also the external crystal oscillator output eco_out and SCB1 alternate functions; max 25 mA per GPIO.
47 XRES input External active-low reset input with an internal pull-up that is always enabled; reset pulse width must be at least 1 µs.
48 VCCD power_out Regulated 1.8 V ±5% digital core supply output; in Mode 1 it must be bypassed to ground with a 0.1 µF X5R ceramic or better capacitor and must not be connected to anything else.
49 VSSD power_in Ground pin for the digital section, to be connected to system ground.
50 VDDD power_in Power supply for the digital section, 1.8 V to 5.5 V in internally regulated mode or 1.71 V to 1.89 V with the regulator bypassed.
51 P5.0 bidirectional Port 5 GPIO bit 0, also TCPWM and SCB2 alternate functions; max 25 mA per GPIO.
52 P5.1 bidirectional Port 5 GPIO bit 1, also TCPWM and SCB2 alternate functions; max 25 mA per GPIO.
53 P5.2 bidirectional Port 5 GPIO bit 2, also TCPWM, LP comparator comp[0] and SCB2 alternate functions; max 25 mA per GPIO.
54 P5.3 bidirectional Port 5 GPIO bit 3, also TCPWM, LP comparator comp[1] and SCB2 alternate functions; max 25 mA per GPIO.
55 P5.5 bidirectional Port 5 GPIO bit 5, also TCPWM and SCB2 alternate functions; max 25 mA per GPIO.
56 VDDA power_in Power supply for the analog section; analog circuits run directly from the VDD input over the 1.71 V to 5.5 V device range.
57 VSSA power_in Ground pin for the analog section, to be connected to system ground.
58 P1.0 bidirectional Port 1 GPIO bit 0, also ctb0_oa0+ opamp input and SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
59 P1.1 bidirectional Port 1 GPIO bit 1, also ctb0_oa0- opamp input and SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
60 P1.2 bidirectional Port 1 GPIO bit 2, also ctb0_oa0_out opamp output and SCB0/SCB2 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
61 P1.3 bidirectional Port 1 GPIO bit 3, also ctb0_oa1_out opamp output and SCB0/SCB2 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
62 P1.4 bidirectional Port 1 GPIO bit 4, also ctb0_oa1- opamp input and SCB0/SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
63 P1.5 bidirectional Port 1 GPIO bit 5, also ctb0_oa1+ opamp input and SCB0/SCB3 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.
64 P1.6 bidirectional Port 1 GPIO bit 6, also ctb0_oa0+ opamp input and SCB0 alternate functions; any GPIO can be configured as CapSense, analog or digital, max 25 mA per GPIO.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package TQFP-64(14x14)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 15
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 15
Maximum current per GPIO IGPIO_ABS -25 25 mA 15
GPIO injection current IGPIO_injection -0.5 0.5 mA Current injected per pin; max for VIH > VDDD, min for VIL < VSS 15
Pin current for latch-up LU -140 140 mA 15
Electrostatic discharge human body model ESD_HBM 2200 V 15
Electrostatic discharge charged device model ESD_CDM 500 V 15
GPIO voltage (max printed as VDD+0.5) VGPIO_ABS -0.5 V 15
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 15
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 15
Execute from flash; CPU at 6 MHz IDD5 1.8 2.4 mA Active Mode, VDD = 1.8 V to 5.5 V 15
Execute from flash; CPU at 24 MHz IDD8 3 4.6 mA Active Mode, VDD = 1.8 V to 5.5 V 15
Execute from flash; CPU at 48 MHz IDD11 5.4 7.1 mA Active Mode, VDD = 1.8 V to 5.5 V 15
I2C wakeup, WDT, and Comparators on IDD17 1.1 1.8 mA Sleep Mode, VDDD = 1.8 V to 5.5 V (regulator on); 6 MHz 15
I2C wakeup, WDT, and Comparators on IDD20 1.5 2.1 mA Sleep Mode, VDDD = 1.8 V to 5.5 V (regulator on); 12 MHz 15
I2C wakeup, WDT, and Comparators on IDD23 1.1 1.8 mA Sleep Mode, VDDD = 1.71 V to 1.89 V (regulator bypassed); 6 MHz 16
I2C wakeup, WDT, and Comparators on IDD23A 1.5 2.1 mA Sleep Mode, VDDD = 1.71 V to 1.89 V (regulator bypassed); 12 MHz 16
I2C wakeup and WDT on IDD25 2.5 40 µA Deep Sleep, VDD = 1.8 V to 3.6 V (regulator on); T = -40 °C to 60 °C 16
I2C wakeup and WDT on IDD26 2.5 125 µA Deep Sleep, VDD = 1.8 V to 3.6 V (regulator on); max at 3.6 V and 85 °C 16
I2C wakeup and WDT on IDD31 2.5 60 µA Deep Sleep, VDD = VCCD = 1.71 V to 1.89 V (regulator bypassed); T = -40 °C to 60 °C 16
I2C wakeup and WDT on IDD32 2.5 180 µA Deep Sleep, VDD = VCCD = 1.71 V to 1.89 V (regulator bypassed); max at 1.89 V and 85 °C 16
Supply current while XRES asserted IDD_XR 2 5 mA 16
CPU frequency FCPU 48 MHz 1.71 V to 5.5 V (VDD) 15
F_SWDCLK1 F_SWDCLK1 14 MHz 3.3 V to 5.5 V (VDD); SWDCLK ≤ 1/3 CPU clock frequency 30
F_SWDCLK2 F_SWDCLK2 7 MHz 1.71 V to 3.3 V (VDD); SWDCLK ≤ 1/3 CPU clock frequency 30
T_SWDO_HOLD T_SWDO_HOLD 1 ns T = 1/f SWDCLK 30
IMO operating current at 48 MHz IIMO1 250 µA Guaranteed by design 30
IMO operating current at 24 MHz IIMO2 180 µA Guaranteed by design 30
Frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % 30
IMO startup time TSTARTIMO 7 µs 30
ILO operating current IILO1 0.3 1.05 µA Guaranteed by design 30
ILO startup time TSTARTILO1 2 ms Guaranteed by design 30
ILO duty cycle TILODUTY 40 50 60 % 30
ILO frequency range FILOTRIM1 20 40 80 kHz 30
Frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 31
Startup time (WCO) TSTART 500 ms 31
Crystal Load Capacitance CL 6 12.5 pF 31
Operating Current (high power mode) IWCO1 8 uA 31
External clock input frequency ExtClkFreq 0 48 MHz 31
Duty cycle ExtClkDuty 45 55 % Measured at VDD/2 31
External clock input frequency (row label as printed for IECO1) IECO1 1.5 mA 31
Crystal frequency range FECO 4 33 MHz 31
PLL current IDD_PLL_48 530 610 uA In = 3 MHz, Out = 48 MHz 31
PLL current IDD_PLL_24 300 405 uA In = 3 MHz, Out = 24 MHz 31
PLL input frequency Fpllin 1 48 MHz 31
PLL intermediate frequency; prescaler out Fpllint 1 3 MHz 31
VCO output frequency before post-divide Fpllvco 22.5 104 MHz 31
Lock time at startup Plllocktime 250 µs 31
Period jitter Jperiod_1 150 ps VCO ≥ 67 MHz; guaranteed by design 31
Period jitter Jperiod_2 200 ps VCO ≤ 67 MHz; guaranteed by design 31
Max delay added by Smart I/O in bypass mode PRG_BYPASS 1.6 ns 32
Block current consumption IDD_CAN 200 µA 32
CAN Bit rate CAN_bits 1 Mbps Min 8-MHz clock 32
Operating junction temperature TJ -40 125 °C 36
Package θJA 64-pin TQFP (0.8-mm pitch) TJA 36.8 °C/Watt 36
Package θJC 64-pin TQFP (0.8-mm pitch) TJC 9.4 °C/Watt 36

CAD (KiCad official)

  • Symbol: CY8C4147AZI-S465
  • Footprint: Package_QFP:TQFP-64_14x14mm_P0.8mm
  • 3D model: TQFP-64(14x14) (KiCad packages3D, STEP)
  • 3D model files: cy8c4147azi-s465-etched.step / cy8c4147azi-s465-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4147azi-s465.step / cy8c4147azi-s465.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (44 pp, sha256 dbd64085f5f9728a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF