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LTC4316IDD#PBF
Public Made by Adomby adom
Analog Devices Global Sourcing Parts, DFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLTC4316IDD#PBF
Analog Devices · Global Sourcing Parts · DFN-10-EP(3x3)
LTC4316IDD#PBF from Analog Devices, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground. |
| 2 | XORH | input | Translator XOR upper-nibble configuration input that sets the upper 3 bits of the address translation byte from a resistive divider between VCC and GND; connect to VCC to activate pass-through mode. |
| 3 | XORL | input | Translator XOR lower-nibble configuration input that sets the lower 4 bits of the address translation byte from a resistive divider between VCC and GND. |
| 4 | VCC | power_in | Power supply input (2.25V to 5.5V); connect to the lower bus supply if input and output supplies differ, and bypass with at least 0.1μF to GND. |
| 5 | ENABLE | input | Enable input; when low address translation is disabled and SDAIN/SCLIN are disconnected from SDAOUT/SCLOUT, a low-to-high transition restarts configuration of the translation byte, and it should be connected to VCC if unused. |
| 6 | READY | output | Open-drain ready status output that releases high when configuration of the translation byte is complete and the input and output buses are connected; use a typical 10k pull-up to the bus supply, and leave open or tie to GND if unused. |
| 7 | SDAIN | bidirectional | Input-bus data input and output connected to the SDA line on the master side; requires an external pull-up resistor or current source. |
| 8 | SDAOUT | bidirectional | Output-bus data input and output connected to the SDA line on the slave side; requires an external pull-up resistor or current source. |
| 9 | SCLOUT | bidirectional | Output-bus clock input and output connected to the SCL line on the slave side; requires an external pull-up resistor or current source. |
| 10 | SCLIN | bidirectional | Input-bus clock input and output connected to the SCL line on the master side; requires an external pull-up resistor or current source. |
| 11 | EP | power_in | Exposed pad (pin 11) is GND; it may be left open or connected to device GND (PCB connection optional). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | DFN-10-EP(3x3) |
| Category | Global Sourcing Parts |
| Pins | 11 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Supply Range | VCC | 2.25 | 5.5 | V | 3 | ||
| Input Supply Current (ENABLE high) | ICC | 0.6 | 2 | mA | ENABLE = 3.3V, SCLIN = SDAIN = 0V | 3 | |
| Input Supply Current (ENABLE low) | ICC | 350 | 800 | μA | ENABLE = 0V, SCLIN = SDAIN = 0V | 3 | |
| VCC Supply Undervoltage Lockout (rising) | VCC(UVLO) | 1.9 | 2.1 | 2.2 | V | VCC Rising | 3 |
| VCC Supply Undervoltage Lockout Hysteresis | VCC(HYST) | 100 | mV | 3 | |||
| ENABLE Threshold Voltage | VENABLE(TH) | 1 | 1.4 | 1.8 | V | ENABLE Rising | 3 |
| ENABLE Hysteresis | VENABLE(HYST) | 50 | mV | 3 | |||
| ENABLE Input Current | IENABLE(LEAK) | -1 | 1 | μA | 3 | ||
| READY Output Low Voltage | VREADY(OL) | 0.4 | V | I = 3mA | 3 | ||
| READY Off Leakage Current | IREADY(OH) | -5 | 5 | μA | VCC = VREADY = 5.5V | 3 | |
| Threshold Voltage (SDA, SCL pins rising) | VSCL,SDA(TH) | 1.5 | 1.8 | 2 | V | SDA, SCL Pins Rising | 3 |
| Threshold Hysteresis (SDA, SCL) | VSCL,SDA(HYST) | 50 | mV | 3 | |||
| Leakage Current (SDA, SCL pins) | ISCL,SDA(LEAK) | -10 | 10 | μA | SDA, SCL Pins = 5.5V, 0V, VCC = 5.5V, 0V | 3 | |
| Input to Output Leakage Current | ISCL,SDA(LEAK-INOUT) | -10 | 10 | μA | SDAIN, SCLIN Pins = 5.5V, VCC = 5.5V, SDAOUT, SCLOUT Pins = 4.5V | 3 | |
| SCL, SDA Pin Capacitance | CSCL,SDA | 10 | pF | Note 3: guaranteed by design, not tested | 3 | ||
| Precharge Voltage | VSCL,SDA(PRE) | 0.8 | 1 | 1.2 | V | 3 | |
| SDAOUT Output Low Voltage | VSDAOUT(OL) | 0.4 | V | I = 4mA | 3 | ||
| Pass Switch On Resistance (VCC = 2.25V) | RDS(ON) | 3 | 12 | Ω | VCC = 2.25V, SCLIN = SDAIN = 0.4V | 3 | |
| Pass Switch On Resistance (VCC = 3.3V) | RDS(ON) | 2.2 | 8 | Ω | VCC = 3.3V, SCLIN = SDAIN = 0.4V | 3 | |
| Pass Switch On Resistance (VCC = 5V) | RDS(ON) | 1.8 | 6 | Ω | VCC = 5V, SCLIN = SDAIN = 0.4V | 3 | |
| XORH and XORL Input Current | IXORH/XORL | -100 | 100 | nA | 3 | ||
| Maximum SCLIN Clock Frequency | fSCL(MAX) | 400 | kHz | Note 3: guaranteed by design, not tested | 3 | ||
| SDAOUT Fall Delay | tPDHL(SDAOUT) | 170 | 300 | ns | C = 100pF, RPULLUP = 10k | 3 | |
| SDAOUT Fall Time | tf(SDAOUT) | 20 | 60 | 300 | ns | C = 100pF, RPULLUP = 10k | 3 |
| Stuck Bus Timeout | tTIMEOUT | 25 | 30 | 35 | ms | SCLIN Held Low or High | 3 |
| Bus Idle Time | tIDLE | 80 | 120 | 160 | μs | 3 | |
| SCLIN and SDAIN Glitch Filter | tGLITCH | 50 | 100 | ns | 3 | ||
| Input Supply Voltage | VCC | -0.3 | 6 | V | 2 | ||
| ENABLE Input Voltage | ENABLE | -0.3 | 6 | V | 2 | ||
| XORL, XORH Input Voltage | XORL, XORH | -0.3 | V | Maximum printed as VCC + 0.3V | 2 | ||
| READY Output Voltage | READY | -0.3 | 6 | V | 2 | ||
| SCLIN, SCLOUT, SDAIN, SDAOUT Input/Output Voltage | -0.3 | 6 | V | 2 | |||
| Output Current (READY, SDAOUT) | 50 | mA | READY, SDAOUT | 2 | |||
| Operating Temperature Range (LTC4316I) | TA | -40 | 85 | °C | LTC4316I grade (this MPN) | 2 | |
| Storage Temperature Range | TSTG | -65 | 150 | °C | 2 | ||
| Maximum Junction Temperature | TJMAX | 150 | °C | 2 | |||
| Thermal Resistance, Junction to Ambient (DD package) | θJA | 43 | °C/W | 10-lead 3mm x 3mm plastic DFN (DD package) | 2 |
CAD (KiCad official)
- Symbol:
LTC4316IDD#PBF - Footprint:
Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm - 3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
ltc4316idd-pbf-etched.step/ltc4316idd-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc4316idd-pbf.step/ltc4316idd-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (16 pp, sha256
fdda8e30a52ebd49, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).