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SN74AUC1G80DBVR

Public Made by Adom

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Texas Instruments Flip Flops, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74AUC1G80DBVR

Texas Instruments · Flip Flops · SOT-23-5

SN74AUC1G80DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D input Data input whose level, when it meets the setup time, is transferred to Q on the positive-going clock edge; unused inputs must be held at VCC or GND.
2 CLK input Positive-edge clock input; triggering occurs at a voltage level and is not directly related to the clock rise time.
3 GND power_in Ground reference for the device.
4 Q output Flip-flop data output with ±8-mA drive at 1.8 V, updated on the positive clock edge.
5 VCC power_in Supply voltage pin, operational from 0.8 V to 2.7 V and designed for 1.65 V to 1.95 V operation.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOT-23-5
Category Logic
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 3.6 V 2
Input voltage range VI -0.5 3.6 V 2
Voltage range applied to any output in the high-impedance or power-off state VO -0.5 3.6 V 2
Output voltage range VO -0.5 V maximum printed as VCC + 0.5 V 2
Input clamp current IIK -50 mA VI < 0 2
Output clamp current IOK -50 mA VO < 0 2
Continuous output current IO -20 20 mA 2
Continuous current through VCC or GND -100 100 mA 2
Storage temperature range Tstg -65 150 °C 2
Supply voltage VCC 0.8 2.7 V 3
High-level input voltage VIH 1.7 V VCC = 2.3 V to 2.7 V 3
Low-level input voltage VIL 0 V VCC = 0.8 V 3
Low-level input voltage VIL 0.7 V VCC = 2.3 V to 2.7 V 3
Input voltage VI 0 3.6 V 3
High-level output current IOH -0.7 mA VCC = 0.8 V 3
High-level output current IOH -3 mA VCC = 1.1 V 3
High-level output current IOH -5 mA VCC = 1.4 V 3
High-level output current IOH -8 mA VCC = 1.65 V 3
High-level output current IOH -9 mA VCC = 2.3 V 3
Low-level output current IOL 0.7 mA VCC = 0.8 V 3
Low-level output current IOL 3 mA VCC = 1.1 V 3
Low-level output current IOL 5 mA VCC = 1.4 V 3
Low-level output current IOL 8 mA VCC = 1.65 V 3
Low-level output current IOL 9 mA VCC = 2.3 V 3
Operating free-air temperature TA -40 85 °C 3
High-level output voltage VOH 0.55 V IOH = -0.7 mA, VCC = 0.8 V 3
High-level output voltage VOH 0.8 V IOH = -3 mA, VCC = 1.1 V 3
High-level output voltage VOH 1 V IOH = -5 mA, VCC = 1.4 V 3
High-level output voltage VOH 1.2 V IOH = -8 mA, VCC = 1.65 V 3
High-level output voltage VOH 1.8 V IOH = -9 mA, VCC = 2.3 V 3
Low-level output voltage VOL 0.2 V IOL = 100 µA, VCC = 0.8 V to 2.7 V 3
Low-level output voltage VOL 0.25 V IOL = 0.7 mA, VCC = 0.8 V 3
Low-level output voltage VOL 0.3 V IOL = 3 mA, VCC = 1.1 V 3
Low-level output voltage VOL 0.4 V IOL = 5 mA, VCC = 1.4 V 3
Low-level output voltage VOL 0.45 V IOL = 8 mA, VCC = 1.65 V 3
Low-level output voltage VOL 0.6 V IOL = 9 mA, VCC = 2.3 V 3
Input current (D or CLK) II -5 5 µA VI = VCC or GND, VCC 0 to 2.7 V 3
Off-state input/output current Ioff -10 10 µA VI or VO = 2.7 V, VCC = 0 3
Supply current ICC 10 µA VI = VCC or GND, IO = 0, VCC 0.8 V to 2.7 V 3
Clock frequency fclock 200 MHz VCC = 1.2 V ±0.1 V 4
Clock frequency fclock 225 MHz VCC = 1.5 V ±0.1 V 4
Clock frequency fclock 250 MHz VCC = 1.8 V ±0.15 V 4
Clock frequency fclock 275 MHz VCC = 2.5 V ±0.2 V 4
Pulse duration, CLK high or low tw 1.7 ns VCC = 1.2 V ±0.1 V 4
Setup time before CLK↑, data high or low tsu 1.1 ns VCC = 1.2 V ±0.1 V 4
Setup time before CLK↑, data high or low tsu 0.8 ns VCC = 1.5 V ±0.1 V 4
Setup time before CLK↑, data high or low tsu 0.6 ns VCC = 1.8 V ±0.15 V 4
Setup time before CLK↑, data high or low tsu 0.5 ns VCC = 2.5 V ±0.2 V 4
Hold time, data after CLK↑ th 0 ns VCC = 1.2 V ±0.1 V 4
Hold time, data after CLK↑ th 0.1 ns VCC = 1.5 V ±0.1 V 4
Propagation delay CLK to Q (CL = 15 pF) tpd 1 3.9 ns CL = 15 pF, VCC = 1.2 V ±0.1 V 4
Propagation delay CLK to Q (CL = 15 pF) tpd 0.8 2.5 ns CL = 15 pF, VCC = 1.5 V ±0.1 V 4
Propagation delay CLK to Q (CL = 15 pF) tpd 0.3 1 1.9 ns CL = 15 pF, VCC = 1.8 V ±0.15 V 4
Propagation delay CLK to Q (CL = 15 pF) tpd 0.3 1.3 ns CL = 15 pF, VCC = 2.5 V ±0.2 V 4
Thermal impedance, junction to ambient, DBV package θJA 206 °C/W DBV package 2

CAD (KiCad official)

  • Symbol: SN74AUC1G80DBVR
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D, STEP)
  • 3D model files: sn74auc1g80dbvr-etched.step / sn74auc1g80dbvr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74auc1g80dbvr.step / sn74auc1g80dbvr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (16 pp, sha256 a7604bbdcd195a3c, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF