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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

DM9161EP

DAVICOM · Ethernet Transceivers · LQFP-48(7x7)

DM9161EP from DAVICOM, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	Analog receive power supply pin; the datasheet specifies a single low-power 3.3V supply.
2	AVDD	power_in	Analog receive power supply pin, connected to the same analog receive supply as pin 1.
3	RX+/FXRD+	input	Positive leg of the differential receive pair from the media; carries pseudo-ECL signal in fiber mode.
4	RX-/FXRD-	input	Negative leg of the differential receive pair from the media; carries pseudo-ECL signal in fiber mode.
5	AGND	power_in	Analog receive ground.
6	AGND	power_in	Analog transmit ground.
7	TX+/FXTD+	output	Positive leg of the differential transmit pair to the media; transmits pseudo-ECL signal in fiber mode.
8	TX-/FXTD-	output	Negative leg of the differential transmit pair to the media; transmits pseudo-ECL signal in fiber mode.
9	AVDD	power_in	Analog transmit power supply pin.
10	PWRDWN	input	Asserted high to force power-down mode, leaving only the MDC/MDIO management logic active; the device leaves power-down only after hardware or software reset with PWRDWN low.
11	FDX/COLLED#/OP0	output	Full-duplex LED output (or full-duplex/collision LED when register 16 bit 5 is set), and OP0 power-up/reset latch input that selects the forced or advertised operating mode per Table A.
12	SPEEDLED#/OP1	output	Speed LED output, active to indicate 100 Mbps mode, and OP1 power-up/reset latch input that selects the operating mode per Table A.
13	LINK/ACTLED#/OP2	output	Link and activity LED output for 10 and 100 Mbps operation, and OP2 power-up/reset latch input that selects the operating mode per Table A.
14	CABLESTS/LINKSTS	output	Cable status output when latched low at power-up (default) or link status output when latched high.
15	DGND	power_in	Digital ground.
16	TXER/TXD[4]	input	Transmit error input in 100 Mbps mode (substitutes HALT when TXEN is active and ignored at 10 Mbps); becomes the fifth TXD data bit TXD[4] in bypass 4B5B mode.
17	TXD[3]	input	MII transmit data bit 3, sampled synchronous to TXCLK in 10/100 Mbps nibble mode and ignored in 10 Mbps GPSI mode.
18	TXD[2]	input	MII transmit data bit 2, sampled synchronous to TXCLK in 10/100 Mbps nibble mode and ignored in 10 Mbps GPSI mode.
19	TXD[1]	input	MII transmit data bit 1, sampled synchronous to TXCLK in 10/100 Mbps nibble mode and ignored in 10 Mbps GPSI mode.
20	TXD[0]	input	MII transmit data bit 0, synchronous to TXCLK; serves as the serial data input in 10 Mbps GPSI (7-wired) mode.
21	TXEN	input	Transmit enable; active high indicates valid nibble data on TXD[0:3] (or valid 10 Mbps data on TXD[0] in GPSI mode).
22	TXCLK/ISOLATE	tri_state	Transmit clock output from the PHY (25 MHz in 100 Mbps nibble mode, 2.5 MHz in 10 Mbps nibble mode, 10 MHz in 10 Mbps GPSI mode); ISOLATE power-up latch sets register 0.10 to 0 or 1.
23	DVDD	power_in	Digital power supply pin.
24	MDC	input	Management Data Clock input from the station management entity, up to 2.5 MHz.
25	MDIO	bidirectional	Bidirectional management data I/O, which may be driven by the station management entity or by the PHY.
26	RXD[3]/PHYAD[3]	tri_state	MII receive data bit 3 output, synchronous to RXCLK in 10/100 Mbps MII mode; also the PHY address bit 3 power-up/reset latch input.
27	RXD[2]/PHYAD[2]	tri_state	MII receive data bit 2 output, synchronous to RXCLK in 10/100 Mbps MII mode; also the PHY address bit 2 power-up/reset latch input.
28	RXD[1]/PHYAD[1]	tri_state	MII receive data bit 1 output, synchronous to RXCLK in 10/100 Mbps MII mode; also the PHY address bit 1 power-up/reset latch input.
29	RXD[0]/PHYAD[0]	tri_state	MII receive data bit 0 output, synchronous to RXCLK; serves as the serial data output in 10 Mbps GPSI mode, and is also the PHY address bit 0 power-up/reset latch input.
30	DVDD	power_in	Digital power supply pin.
31	RXEN	input	Active high enables RXD[0:3], RXCLK, and RXDV outputs; active low tri-states these outputs; pull high in node applications.
32	MDINTR#	output	Active-low status interrupt output asserted on any link, speed, or duplex change; it is high-impedance and requires a 2.2 kΩ pull-up resistor.
33	DGND	power_in	Digital ground.
34	RXCLK/SCRAMEN/10BTSER	tri_state	Receive clock output from the PHY (25 MHz in 100 Mbps MII, 2.5 MHz in 10 Mbps MII, 10 MHz in 10 Mbps GPSI); power-up latch selects scrambler enable or 10 Mbps serial mode, and is only supported in forced 100M or 10M modes.
35	CRS/PHYAD[4]	tri_state	Carrier sense output asserted high for carrier due to receive or transmit activity in half-duplex mode (receive only in full-duplex or repeater mode); also the PHY address bit 4 power-up/reset latch input.
36	COL/RMII	tri_state	Collision detect output asserted high in 10/100 Mbps half-duplex mode (always low in full-duplex); power-up latch selects Reduced MII when high (default low for Normal MII).
37	RXDV/TESTMODE	tri_state	Receive data valid output asserted high when valid data is presented on RXD[0:3]; power-up latch enables test mode when high (default 0, normal operation).
38	RXER/RXD[4]/RPTR	tri_state	Receive error output asserted high on invalid symbol detection; becomes RXD[4] in decoder bypass mode; power-up latch selects Repeater mode when high or Node mode when low (default).
39	DVDD	power_in	Digital power supply pin.
40	RESET#	input	Active-low input that initializes the DM9161 when asserted.
41	DVDD	power_in	Digital power supply pin.
42	XT2	bidirectional	Crystal output (25 MHz crystal in normal MII mode); serves as the REF_CLK input (50 MHz) in RMII mode.
43	XT1	input	Crystal input (25 MHz crystal in normal MII and GPSI modes; floating in RMII mode).
44	DGND	power_in	Digital ground.
45	SD	input	Fiber-optic PECL signal detect input, indicating whether the fiber receive pair is receiving valid signal levels.
46	AGND	power_in	Analog substrate ground.
47	BGRESG	power_in	Bandgap ground.
48	BGRES	output	Bandgap voltage reference resistor connection; a 6.8 kΩ resistor is used here.

Key specifications

Parameter	Value
Manufacturer	DAVICOM
Package	LQFP-48(7x7)
Category	Interface
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
DVDD, AVDD Supply Voltage (absolute maximum)	DVDD, AVDD	-0.3		3.6	V		33
DC Input Voltage (absolute maximum)	VIN	-0.5		5.5	V		33
DC Output Voltage (absolute maximum)	VOUT	-0.3		3.6	V		33
Storage Temperature Range	Tstg	-65		150	°C		33
Lead Temp. (TL, Soldering, 10 sec.)	LT			260	°C	Pb-Free	33
DVDD, AVDD Supply Voltage (operating)	DVDD,AVDD	3.135		3.465	V		33
Ambient Temperature	TA			70	°C		33
Power Dissipation, 100BASE-TX	PD			88	mA	3.3V	33
Power Dissipation, 100BASE-FX	PD			25	mA	3.3V	33
Power Dissipation, 10BASE-T TX	PD			70	mA	3.3V; 10BASE-T TX, normal activity traffic 50% utility	33
Power Dissipation, 10BASE-T idle	PD			30	mA	3.3V	33
Power Dissipation, Auto-negotiation	PD			45	mA	3.3V	33
Power Dissipation, Power Reduced Mode (without cable)	PD			18	mA	3.3V	33
Power Dissipation, Power Down Mode	PD			3	mA	3.3V	33
TTL Input Low Voltage	VIL			0.8	V		34
TTL Input High Voltage	VIH	2			V		34
TTL Input Low Leakage Current	IIL			10	uA	VIN = 0.4V	34
TTL Input High Leakage Current	IIH			-10	uA	VIN = 2.7V	34
MII TTL Output Low Voltage	VOL			0.4	V	IOL = 4mA	34
MII TTL Output High Voltage	VOH	2.4			V	IOH = -4mA	34
Non-MII TTL Output Low Voltage	VOL			0.4	V	IOL = 2mA	34
Non-MII TTL Output High Voltage	VOH	2.4			V	IOH = -2mA	34
100TX+/- Differential Output Voltage	VTD100	1.9	2	2.1	V	Peak to Peak	34
100TX+/- Differential Output Current	ITD100	19	20	21	mA		34
100FX+/- Differential Output Current	IFD100	17	18	19	mA		34
100TX+/- Differential Rise/Fall Time	tTR/F	3		5	ns		34
100TX+/- Differential Rise/Fall Time Mismatch	tTM	0		0.5	ns		34
100TX+/- Differential Output Duty Cycle Distortion	tTDC	0		0.5	ns		34
100TX+/- Differential Output Peak-to-Peak Jitter	tT/T	0		1.4	ns		34
100TX+/- Differential Voltage Overshoot	XOST	0		5	%		34
OSC Cycle Time	tCKC	39.998	40	40.002	ns	50ppm	35
OSC Pulse Width High	tPWH	16	20	24	ns		35
OSC Pulse Width Low	tPWL	16	20	24	ns		35
MDC Cycle Time	t0	80			ns		35
MDIO Setup Before MDC	t1	10			ns	When OUTPUT By STA	35
MDIO Hold After MDC	t2	10			ns	When OUTPUT By STA	35
MDC To MDIO Output Delay	t3	0		300	ns	When OUTPUT By DM9161	35

CAD (KiCad official)

Symbol: DM9161EP
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: dm9161ep-etched.step / dm9161ep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); dm9161ep.step / dm9161ep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: DAVICOM datasheet (50 pp, sha256 0126968b71ebf164, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF