component
SN74LS74N
Public Made by Adomby adom
lingxingic Flip Flops, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LS74N
lingxingic · Flip Flops · DIP-14
SN74LS74N from lingxingic, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ~{1RD} | input | Asynchronous reset input for flip-flop 1, active low (1R̄D on the datasheet). |
| 2 | 1D | input | Data input for flip-flop 1, sampled on the rising clock edge. |
| 3 | 1CP | input | Clock input for flip-flop 1, edge-triggered on the low-to-high transition. |
| 4 | ~{1SD} | input | Asynchronous set input for flip-flop 1, active low (1S̄D on the datasheet). |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | ~{1Q} | output | Inverted (complementary) output of flip-flop 1. |
| 7 | GND | power_in | Ground reference, 0 V. |
| 8 | ~{2Q} | output | Inverted (complementary) output of flip-flop 2. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | ~{2SD} | input | Asynchronous set input for flip-flop 2, active low (2S̄D on the datasheet). |
| 11 | 2CP | input | Clock input for flip-flop 2, edge-triggered on the low-to-high transition. |
| 12 | 2D | input | Data input for flip-flop 2, sampled on the rising clock edge. |
| 13 | ~{2RD} | input | Asynchronous reset input for flip-flop 2, active low (2R̄D on the datasheet). |
| 14 | VCC | power_in | Supply voltage; the recommended range is 2.0 V to 6.0 V with 5.0 V typical. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 8 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI<-0.5V or VI>VCC+0.5V | 8 | |
| Output clamp current | IOK | -20 | 20 | mA | VO<-0.5V or VO>VCC+0.5V | 8 | |
| Output current | IO | -25 | 25 | mA | -0.5V<VO<VCC+0.5V | 8 | |
| Supply current | ICC | 100 | mA | 8 | |||
| Ground current | IGND | -100 | mA | 8 | |||
| Total power dissipation | Ptot | 500 | mW | 8 | |||
| Storage temperature | Tstg | -65 | 150 | ℃ | 8 | ||
| Soldering temperature | TL | 245 | ℃ | 10 s; DIP package | 8 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 8 | |
| Input voltage | VI | 0 | V | 8 | |||
| Output voltage | VO | 0 | V | 8 | |||
| Input rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 8 | ||
| Input rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 8 | |
| Input rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 8 | ||
| Operating ambient temperature | Tamb | -40 | 125 | ℃ | 8 | ||
| High-level input voltage | VIH | 1.5 | 1.2 | V | Tamb=-40℃~+85℃; VCC=2.0V | 9 | |
| High-level input voltage | VIH | 3.15 | 2.4 | V | Tamb=-40℃~+85℃; VCC=4.5V | 9 | |
| High-level input voltage | VIH | 4.2 | 3.2 | V | Tamb=-40℃~+85℃; VCC=6.0V | 9 | |
| Low-level input voltage | VIL | 0.8 | 0.5 | V | Tamb=-40℃~+85℃; VCC=2.0V | 9 | |
| Low-level input voltage | VIL | 2.1 | 1.35 | V | Tamb=-40℃~+85℃; VCC=4.5V | 9 | |
| Low-level input voltage | VIL | 2.8 | 1.8 | V | Tamb=-40℃~+85℃; VCC=6.0V | 9 | |
| High-level output voltage | VOH | 3.84 | 4.32 | V | Tamb=-40℃~+85℃; VI=VIH or VIL; IO=-4.0mA; VCC=4.5V | 9 | |
| High-level output voltage | VOH | 5.34 | 5.81 | V | Tamb=-40℃~+85℃; VI=VIH or VIL; IO=-5.2mA; VCC=6.0V | 9 | |
| Low-level output voltage | VOL | 0.15 | 0.33 | V | Tamb=-40℃~+85℃; VI=VIH or VIL; IO=4.0mA; VCC=4.5V | 9 | |
| Low-level output voltage | VOL | 0.16 | 0.33 | V | Tamb=-40℃~+85℃; VI=VIH or VIL; IO=5.2mA; VCC=6.0V | 9 | |
| Input leakage current | II | -1 | 1 | uA | Tamb=-40℃~+85℃; VI=VCC or GND; VCC=6.0V | 9 | |
| Static supply current | ICC | 40 | uA | Tamb=-40℃~+85℃; VI=VCC or GND; IO=0A; VCC=6.0V | 9 | ||
| nCP to nQ, nQ propagation delay | tpd | 47 | 220 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=2.0V | 11 | |
| nCP to nQ, nQ propagation delay | tpd | 17 | 44 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=4.5V | 11 | |
| nCP to nQ, nQ propagation delay | tpd | 14 | 37 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=6.0V | 11 | |
| nSD to nQ, nQ propagation delay | tpd | 50 | 250 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=2.0V | 11 | |
| nSD to nQ, nQ propagation delay | tpd | 18 | 50 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=4.5V | 11 | |
| nSD to nQ, nQ propagation delay | tpd | 14 | 43 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=6.0V | 11 | |
| nRD to nQ, nQ propagation delay | tpd | 52 | 250 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=2.0V | 11 | |
| nRD to nQ, nQ propagation delay | tpd | 19 | 50 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=4.5V | 11 | |
| nRD to nQ, nQ propagation delay | tpd | 15 | 43 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=6.0V | 11 | |
| nQ, nQ transition time | tt | 19 | 95 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=2.0V | 11 | |
| nQ, nQ transition time | tt | 7 | 19 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=4.5V | 11 | |
| nQ, nQ transition time | tt | 6 | 16 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=6.0V | 11 | |
| CP pulse width | tW | 100 | 19 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=2.0V | 11 | |
| CP pulse width | tW | 20 | 7 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=4.5V | 11 | |
| CP pulse width | tW | 17 | 6 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=6.0V | 11 | |
| nSD, nRD pulse width | tW | 100 | 19 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=2.0V | 11 | |
| nSD, nRD pulse width | tW | 20 | 7 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=4.5V | 11 | |
| nSD, nRD pulse width | tW | 17 | 6 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=6.0V | 11 | |
| nSD, nRD recovery time | trec | 40 | 3 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=2.0V | 11 | |
| nSD, nRD recovery time | trec | 8 | 1 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=4.5V | 11 | |
| nSD, nRD recovery time | trec | 7 | 1 | ns | Tamb=-40℃~+85℃; see Fig.7; VCC=6.0V | 11 | |
| nD to nCP setup time | tsu | 75 | 6 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=2.0V | 11 | |
| nD to nCP setup time | tsu | 15 | 2 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=4.5V | 11 | |
| nD to nCP setup time | tsu | 13 | 2 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=6.0V | 11 | |
| nD to nCP hold time | th | 3 | -6 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=2.0V | 11 | |
| nD to nCP hold time | th | 3 | -2 | ns | Tamb=-40℃~+85℃; see Fig.6; VCC=4.5V | 11 | |
| nCP maximum frequency | fmax | 4.8 | 23 | MHz | Tamb=-40℃~+85℃; see Fig.6; VCC=2.0V | 11 | |
| nCP maximum frequency | fmax | 24 | 69 | MHz | Tamb=-40℃~+85℃; see Fig.6; VCC=4.5V | 11 | |
| nCP maximum frequency | fmax | 28 | 82 | MHz | Tamb=-40℃~+85℃; see Fig.6; VCC=6.0V | 11 |
CAD (KiCad official)
- Symbol:
SN74LS74N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ls74n-etched.step/sn74ls74n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ls74n.step/sn74ls74n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (20 pp, sha256
3b7790b104e063fb, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).