Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

AiP74HC165DA.TB

Wuxi I-core Elec · Shifting Register · DIP-16

AiP74HC165DA.TB from Wuxi I-core Elec, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PL input Asynchronous parallel load input, active LOW; when LOW data from D0 to D7 is loaded into the register.
2 CP input Clock input, LOW-to-HIGH edge-triggered; a HIGH on CE disables it.
3 D4 input Parallel data input 4.
4 D5 input Parallel data input 5.
5 D6 input Parallel data input 6.
6 D7 input Parallel data input 7.
7 ~{Q7} output Complementary output from the last stage.
8 GND power_in Ground (0V).
9 Q7 output Serial output from the last stage.
10 DS input Serial data input.
11 D0 input Parallel data input 0.
12 D1 input Parallel data input 1.
13 D2 input Parallel data input 2.
14 D3 input Parallel data input 3.
15 CE input Clock enable input, active LOW; a HIGH disables the CP input.
16 VCC power_in Supply voltage, 2.0V to 6.0V recommended for AiP74HC165 (absolute maximum 7V).

Key specifications

Parameter Value
Manufacturer Wuxi I-core Elec
Package DIP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 8
Input clamping current IIK 20 mA VI < -0.5V or VI > VCC+0.5V (±20) 8
Output clamping current IOK 20 mA VO < -0.5V or VO > VCC+0.5V (±20) 8
Output current IO 25 mA -0.5V < VO < VCC+0.5V (±25) 8
Supply current ICC 50 mA 8
Ground current IGND -50 mA 8
Total power dissipation Ptot 500 mW DIP16: above 70℃ derates linearly with 12mW/K 8
Storage temperature Tstg -65 150 ℃ 8
Soldering temperature (DIP) TL 245 ℃ 10s, DIP 8
Supply voltage VCC 2 5 6 V AiP74HC165 8
Input voltage VI 0 V AiP74HC165; max = VCC 8
Output voltage VO 0 V AiP74HC165; max = VCC 8
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC=2.0V 8
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC=4.5V 8
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC=6.0V 8
Ambient temperature Tamb -40 85 ℃ 8
HIGH-level input voltage VIH 1.5 1.2 V Tamb=25℃; VCC=2.0V 9
HIGH-level input voltage VIH 3.15 2.4 V Tamb=25℃; VCC=4.5V 9
HIGH-level input voltage VIH 4.2 3.2 V Tamb=25℃; VCC=6.0V 9
LOW-level input voltage VIL 0.8 0.5 V Tamb=25℃; VCC=2.0V 9
LOW-level input voltage VIL 2.1 1.35 V Tamb=25℃; VCC=4.5V 9
LOW-level input voltage VIL 2.8 1.8 V Tamb=25℃; VCC=6.0V 9
HIGH-level output voltage VOH 1.9 2 V Tamb=25℃; VI = VIH or VIL; IO=-20uA; VCC=2.0V 9
HIGH-level output voltage VOH 4.4 4.5 V Tamb=25℃; VI = VIH or VIL; IO=-20uA; VCC=4.5V 9
HIGH-level output voltage VOH 5.9 6 V Tamb=25℃; VI = VIH or VIL; IO=-20uA; VCC=6.0V 9
HIGH-level output voltage VOH 3.98 4.32 V Tamb=25℃; VI = VIH or VIL; IO=-4.0mA; VCC=4.5V 9
HIGH-level output voltage VOH 5.48 5.81 V Tamb=25℃; VI = VIH or VIL; IO=-5.2mA; VCC=6.0V 9
LOW-level output voltage VOL 0 0.1 V Tamb=25℃; VI = VIH or VIL; IO=20uA; VCC=2.0V 9
LOW-level output voltage VOL 0.15 0.26 V Tamb=25℃; VI = VIH or VIL; IO=4.0mA; VCC=4.5V 9
LOW-level output voltage VOL 0.16 0.26 V Tamb=25℃; VI = VIH or VIL; IO=5.2mA; VCC=6.0V 9
Input leakage current II -0.1 0.1 uA Tamb=25℃; VI= VCC or GND; VCC=6.0V (±0.1) 9
Supply current ICC 8 uA Tamb=25℃; VI= VCC or GND; IO=0A; VCC=6.0V 9
HIGH-level input voltage VIH 3.15 V Tamb=-40℃ to +85℃; VCC=4.5V 10
LOW-level input voltage VIL 1.35 V Tamb=-40℃ to +85℃; VCC=4.5V 10
HIGH-level output voltage VOH 3.84 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-4.0mA; VCC=4.5V 10
HIGH-level output voltage VOH 5.34 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=-5.2mA; VCC=6.0V 10
LOW-level output voltage VOL 0.33 V Tamb=-40℃ to +85℃; VI = VIH or VIL; IO=4.0mA; VCC=4.5V 10
Input leakage current II -1 1 uA Tamb=-40℃ to +85℃; VI=VCC or GND; VCC=6.0V (±1) 10
Supply current ICC 80 uA Tamb=-40℃ to +85℃; VI=VCC or GND; IO=0A; VCC=6.0V 10
Propagation delay CP, CE to Q7, Q7bar tpd 19 33 ns Tamb=25℃; CL=50pf; VCC=4.5V; see Figure 6 11
Propagation delay PL to Q7, Q7bar tpd 18 33 ns Tamb=25℃; CL=50pf; VCC=4.5V; see Figure 7 11
Maximum frequency CP input fmax 30 51 MHz Tamb=25℃; VCC=4.5V; see Figure 6 11
Propagation delay CP, CE to Q7, Q7bar tpd 41 ns Tamb=-40℃ to +85℃; CL=50pf; VCC=4.5V; see Figure 6 13
Propagation delay PL to Q7, Q7bar tpd 41 ns Tamb=-40℃ to +85℃; CL=50pf; VCC=4.5V; see Figure 7 13
Propagation delay D7 to Q7, Q7bar tpd 30 ns Tamb=-40℃ to +85℃; CL=50pf; VCC=4.5V; see Figure 8 13
Transition time Q7, Q7bar output tt 19 ns Tamb=-40℃ to +85℃; CL=50pf; VCC=4.5V; see Figure 6 13
Pulse width CP input HIGH or LOW tW 20 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 13
Pulse width PL input LOW tW 20 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 13
Recovery time PL to CP, CE trec 25 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 13
Set-up time DS to CP, CE tsu 20 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 9 13
Set-up time CE to CP and CP to CE tsu 20 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 9 13
Set-up time Dn to PL tsu 20 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 10 13
Hold time DS to CP, CE and Dn to PL th 5 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 9 13
Hold time CE to CP and CP to CE th 5 ns Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 9 13
Maximum frequency CP input fmax 24 MHz Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 14
Input capacitance CI 3.5 pF Tamb=25℃ 9
Power dissipation capacitance CPD 35 pF per package; VI= GND to VCC 12

CAD (KiCad official)

  • Symbol: AiP74HC165DA.TB
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: aip74hc165da-tb-etched.step / aip74hc165da-tb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); aip74hc165da-tb.step / aip74hc165da-tb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Wuxi I-core Elec datasheet (21 pp, sha256 bc3dffc92a351153, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF