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SN74HC194 Universal Shift Register

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by Ray

4-bit bidirectional universal shift register with parallel load and shift-left/right control.

logicshift-registerbidirectionaluniversal74hctisoic-16
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Contents

README

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SN74HC194

Texas Instruments · Shift Register · SOIC-16

The SN74HC194 is a 4-bit bidirectional universal shift register. Two mode-control inputs select shift-left, shift-right, parallel load, or hold, with separate serial inputs for each shift direction and an active-low clear. It is used for serial/parallel conversion and data movement in either direction.

Pinout

Pin Name Type Function
1 MR input Asynchronous Master Reset, active-low. When driven low, all four internal flip-flops are cleared and Q0-Q3 are forced to logic Low regardless of the clock. Minimum MR pulse width is 16ns at VCC=4.5V.
2 DSR input Serial data input for shift-right mode. The logic level on DSR is clocked into Q0 on the rising edge of CP when S1=Low, S0=High.
3 D0 input Parallel data input D0. Loaded into flip-flop Q0 on the rising edge of CP when S0=High and S1=High (parallel load mode).
4 D1 input Parallel data input D1. Loaded into flip-flop Q1 on the rising edge of CP when S0=High and S1=High (parallel load mode).
5 D2 input Parallel data input D2. Loaded into flip-flop Q2 on the rising edge of CP when S0=High and S1=High (parallel load mode).
6 D3 input Parallel data input D3. Loaded into flip-flop Q3 on the rising edge of CP when S0=High and S1=High (parallel load mode).
7 DSL input Serial data input for shift-left mode. The logic level on DSL is clocked into Q3 on the rising edge of CP when S1=High, S0=Low.
8 GND power_in Ground reference (0V) for the device.
9 S0 input Mode select input S0. Combined with S1 selects one of four operating modes: hold (S1=L,S0=L), shift-right (S1=L,S0=H), shift-left (S1=H,S0=L), parallel load (S1=H,S0=H).
10 S1 input Mode select input S1. See S0 for the mode encoding table.
11 CP input Clock input. All synchronous operations (shift-right, shift-left, parallel-load, hold) occur on the rising (Low-to-High) edge of CP. Typical fMAX = 60MHz at VCC=5V, CL=15pF.
12 Q3 output Parallel output Q3, the MSB of the shift register. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low.
13 Q2 output Parallel output Q2. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low.
14 Q1 output Parallel output Q1. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low.
15 Q0 output Parallel output Q0, the LSB of the shift register. Drives standard-output loads (10 LSTTL). Cleared to Low on MR=Low.
16 VCC power_in Positive supply voltage. 2V to 6V for HC types, 4.5V to 5.5V for HCT types. Bypass with a 100nF ceramic capacitor close to the pin.

Key specifications

Parameter Value
Type 4-bit bidirectional universal shift register
Logic family 74HC (CMOS)
Modes Shift left, shift right, parallel load, hold
Clear Active-low, asynchronous
Supply voltage 2 V to 6 V
Max clock 50 MHz typ at 5 V
Operating temperature -40 C to 85 C

Ordering variants

Same part, different packaging or reel option.

  • SN74HC194E
  • SN74HC194M
  • SN74HC194MT
  • SN74HC194M96
  • SN74HC194NSR
  • SN74HC194PW
  • SN74HC194PWR
  • SN74HC194PWT
  • SN74HC194F3A

CAD (KiCad official)

  • Symbol: sn74hc194.kicad_sym
  • Footprint: sn74hc194.kicad_mod
  • 3D model: SOIC-16 body from KiCad Package_SO/SOIC-16_3.9x9.9mm_P1.27mm.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (19 pp, sha256 209a444fe7a9beeb, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF