component
ZJC2544-16BSDBR
Public Made by Adomby adom
ZJW Digital To Analog Converters (DACs), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownZJC2544-16BSDBR
ZJW · Digital To Analog Converters (DACs) · SOIC-14
ZJC2544-16BSDBR from ZJW, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | RFB | input | Feedback resistor input pin; connect it to the external amplifier output for bipolar mode. |
| 2 | VOUT | output | DAC un-buffered voltage output with a typical output resistance of 6.25 kΩ. |
| 3 | AGNDF | power_in | Analog ground force pin. |
| 4 | AGNDS | power_in | Analog ground sense pin. |
| 5 | REFS | output | Voltage reference sense output. |
| 6 | REFF | input | Voltage reference force input. |
| 7 | CS | input | Serial digital chip select input, active low. |
| 8 | SCLK | input | Serial data clock input. |
| 9 | NC | unconnected | No connection. |
| 10 | DIN | input | Serial digital data input. |
| 11 | LDAC | input | When taken low, the DAC register is simultaneously updated with the contents of the input register. |
| 12 | DGND | power_in | Digital ground. |
| 13 | INV | output | Connected to the middle point of the internal scaling resistors; connect to the external op amp inverting input in bipolar mode. |
| 14 | VDD | power_in | Supply voltage input (2.7 V to 5.5 V single supply). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | ZJW |
| Package | SOIC-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Nonlinear Error (16 bits) | INL | -1 | 0.5 | 1 | LSB | 16 bits, full temperature range | 9 |
| Differential Nonlinear Error (16 bits) | DNL | -0.75 | 0.25 | 0.75 | LSB | 16 bits, full temperature range | 9 |
| Gain Error (16 bits) | GE | -0.75 | 0.3 | 0.75 | LSB | 16 bits, TA=25 °C | 9 |
| Gain Error (16 bits) | GE | -1 | 0.5 | 1 | LSB | 16 bits, -40 °C≤TA≤+85 °C | 9 |
| Gain Error (16 bits) | GE | -1.5 | 0.5 | 1.5 | LSB | 16 bits, -40 °C≤TA≤+125 °C | 9 |
| Zero Code Error (16 bits) | ZCE | -1 | 0.25 | 1 | LSB | 16 bits, full temperature range | 9 |
| Bipolar Zero Code Error (16-bit) | -4 | 1 | 4 | LSB | 16-bit, full temperature range | 9 | |
| Reference Input Voltage Range | 2 | V | full temperature range; max printed as VDD | 10 | |||
| Reference Input Resistance, Unipolar | 8 | kΩ | Unipolar | 10 | |||
| Reference Input Resistance, Bipolar | 6 | kΩ | Bipolar | 10 | |||
| Input High Voltage | VIH | 2.4 | V | full temperature range; printed 2.4/0.9*VLOGIC | 10 | ||
| Input Low Voltage | VIL | 0.8 | V | full temperature range; printed 0.8/0.1*VLOGIC | 10 | ||
| Input Current | -1 | 1 | µA | full temperature range | 10 | ||
| Power Supply | VDD | 2.7 | 5.5 | V | full temperature range | 11 | |
| Digital Interface Power | VLOGIC | 1.8 | 5.5 | V | 11 | ||
| Rated Performance Temperature Range | TMIN to TMAX | -40 | 125 | °C | 11 | ||
| Supply Current | IVDD | 120 | µA | VDD=5 V | 11 | ||
| SCLK Frequency (1.8 V≤VLOGIC<2.7 V) | fSCLK | 14 | MHz | 1.8 V≤VLOGIC<2.7 V | 12 | ||
| SCLK Frequency (2.7 V≤VLOGIC≤5.5 V) | fSCLK | 50 | MHz | 2.7 V≤VLOGIC≤5.5 V | 12 | ||
| SCLK Period (1.8 V≤VLOGIC<2.7 V) | t1 | 70 | ns | 1.8 V≤VLOGIC<2.7 V | 12 | ||
| SCLK Period (2.7 V≤VLOGIC≤5.5 V) | t1 | 20 | ns | 2.7 V≤VLOGIC≤5.5 V | 12 | ||
| SCLK High Level Time (1.8 V≤VLOGIC<2.7 V) | t2 | 35 | ns | 1.8 V≤VLOGIC<2.7 V | 12 | ||
| SCLK High Level Time (2.7 V≤VLOGIC≤5.5 V) | t2 | 9 | ns | 2.7 V≤VLOGIC≤5.5 V | 12 | ||
| SCLK Low Level Time (1.8 V≤VLOGIC<2.7 V) | t3 | 35 | ns | 1.8 V≤VLOGIC<2.7 V | 12 | ||
| SCLK Low Level Time (2.7 V≤VLOGIC≤5.5 V) | t3 | 9 | ns | 2.7 V≤VLOGIC≤5.5 V | 12 | ||
| CS Low To SCLK High Setup Time | t4 | 5 | ns | both VLOGIC ranges | 12 | ||
| CS High To SCLK High Setup Time | t5 | 50 | ns | both VLOGIC ranges | 12 | ||
| SCLK High To CS Low Hold Time | t6 | 5 | ns | both VLOGIC ranges | 12 | ||
| SCLK High To CS High Hold Time (1.8 V≤VLOGIC<2.7 V) | t7 | 10 | ns | 1.8 V≤VLOGIC<2.7 V | 12 | ||
| SCLK High To CS High Hold Time (2.7 V≤VLOGIC≤5.5 V) | t7 | 5 | ns | 2.7 V≤VLOGIC≤5.5 V | 12 | ||
| Data Creation Time (1.8 V≤VLOGIC<2.7 V) | t8 | 35 | ns | 1.8 V≤VLOGIC<2.7 V | 12 | ||
| Data Creation Time (2.7 V≤VLOGIC≤5.5 V) | t8 | 10 | ns | 2.7 V≤VLOGIC≤5.5 V | 12 | ||
| Data Hold Time | t9 | 5 | ns | VINH=90% of VDD, VINL=10% of VDD | 12 | ||
| CS High Time Between Low Levels | t10 | 15 | ns | both VLOGIC ranges | 12 | ||
| LDAC Low Pulse Width | t11 | 20 | ns | both VLOGIC ranges | 12 | ||
| CS High To LDAC Low Settling Time | t12 | 10 | ns | both VLOGIC ranges | 12 | ||
| LDAC Low To SCLK High Setup Time | t13 | 60 | ns | both VLOGIC ranges | 12 | ||
| VDD to AGND | VDD | -0.3 | 6 | V | 8 | ||
| REF to AGND | REF | -0.3 | V | max printed as VDD+0.3 V | 8 | ||
| Digital Input to DGND | -0.3 | V | max printed as VDD+0.3 V | 8 | |||
| Input current to pins except VDD | -10 | 10 | mA | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature | 150 | °C | 8 | ||||
| Lead Temperature (Soldering, 10 seconds) | 300 | °C | 8 | ||||
| Maximum Reflow Temperature | 260 | °C | IPC/JEDEC J-STD-020 compliant | 8 | |||
| ESD Human Body Model | HBM | 3.5 | kV | 8 | |||
| ESD Charged Device Model | CDM | 2 | kV | 8 | |||
| Thermal Resistance Junction-to-Ambient, SOIC-14 | θJA | 106.7 | °C/W | SOIC-14 | 8 | ||
| Thermal Resistance Junction-to-Case, SOIC-14 | θJC | 54.2 | °C/W | SOIC-14 | 8 | ||
| Gain Error Temperature Drift | -0.05 | 0.05 | ppm/°C | 9 | |||
| Zero Code Error Temperature Coefficient | -0.1 | 0.1 | ppm/°C | 9 | |||
| Bipolar Zero Code Error Drift | -0.1 | 0.1 | ppm/°C | 10 | |||
| Bipolar Resistor Matching | RFB/RINV | -80 | 20 | 80 | ppm | typically RFB=RINV=28 kΩ | 9 |
CAD (KiCad official)
- Symbol:
ZJC2544-16BSDBR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
zjc2544-16bsdbr-etched.step/zjc2544-16bsdbr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);zjc2544-16bsdbr.step/zjc2544-16bsdbr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: ZJW datasheet (30 pp, sha256
57c444aa1bdf9373, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).