component
MCP14700-E
Public Made by Adomby adom
Microchip Tech Pre-ordered Chips, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownMCP14700-E
Microchip Tech · Pre-ordered Chips · SOIC-8
MCP14700-E from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PHASE | passive | Switch node that returns the high-side gate driver current and connects the high-side MOSFET source to the low-side MOSFET drain; VPHASE is limited to VBOOT - 7V to VBOOT + 0.3V. |
| 2 | PWMHI | input | High-side PWM control input where a logic high drives HIGHDR high; the rising threshold is 1.40V to 1.80V and the falling threshold is 1.10V to 1.30V at VCC = 5.0V, and the pin is internally pulled low. |
| 3 | PWMLO | input | Low-side PWM control input where a logic high drives LOWDR high; the rising threshold is 1.40V to 1.80V and the falling threshold is 1.10V to 1.30V at VCC = 5.0V, and the pin is internally pulled low. |
| 4 | GND | power_in | Ground for the MCP14700 circuitry, which should have a low-impedance connection to the bias supply return because high peak currents flow out of this pin when the low-side MOSFET turns off. |
| 5 | LOWDR | output | Low-side gate drive output that controls the low-side MOSFET, with VLOWDR limited to -0.3V to VCC + 0.3V and 2.0A typical source and 3.5A typical sink peak current. |
| 6 | VCC | power_in | Supply input with an operating range of 4.5V to 5.5V (5.0V typical) and an absolute maximum of +7.0V, requiring a bypass capacitor placed as close as possible to this pin and GND. |
| 7 | BOOT | power_in | Floating bootstrap supply for the high-side driver, rated to a maximum of +36.0V, with a bootstrap capacitor connected between this pin and PHASE. |
| 8 | HIGHDR | output | High-side gate drive output that controls the high-side MOSFET, with VHIGHDR limited to VPHASE - 0.3V to VBOOT + 0.3V and 2.0A typical source and 2.0A typical sink peak current. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCC | VCC | -0.3 | 7 | V | 5 | ||
| Boot voltage VBOOT | VBOOT | -0.3 | 36 | V | 5 | ||
| PWM input voltage VPWM | VPWM | -0.3 | V | Maximum printed as VCC + 0.3V | 5 | ||
| LOWDR output voltage VLOWDR | VLOWDR | -0.3 | V | Maximum printed as VCC + 0.3V | 5 | ||
| VCC Operating Range | VCC | 4.5 | 5 | 5.5 | V | 5 | |
| Specified Temperature Range | TA | -40 | 125 | °C | 6 | ||
| Maximum Junction Temperature | TJ | 150 | °C | 6 | |||
| Storage Temperature | TA | -65 | 150 | °C | 6 | ||
| UVLO (Rising VCC) | VUVLO | 3.5 | 4 | V | 5 | ||
| PWM Input Current | IPWM | 7 | 10 | µA | VPWM = 3.0V | 5 | |
| PWMHI Rising Threshold | PWMHI_TH | 1.4 | 1.6 | 1.8 | V | VCC = 5.0V | 5 |
| PWMLO Falling Threshold | PWMLO_TH | 1.1 | 1.2 | 1.3 | V | VCC = 5.0V | 5 |
| Low Output Voltage (HIGHDR and LOWDR) | VOL | 0.025 | V | VCC = 5.0V | 5 | ||
| High Drive Source Resistance | RHI_SRC | 1 | 2.5 | Ω | 500 mA source current, Note 1 | 5 | |
| High Drive Sink Resistance | RHI_SINK | 1 | 2.5 | Ω | 500 mA sink current, Note 1 | 5 | |
| High Drive Source Current | IHI_SRC | 2 | A | Note 1 | 5 | ||
| High Drive Sink Current | IHI_SINK | 2 | A | Note 1 | 5 | ||
| Low Drive Source Resistance | RLO_SRC | 1 | 2.5 | Ω | 500 mA source current, Note 1 | 5 | |
| Low Drive Sink Resistance | RLO_SINK | 0.5 | 1 | Ω | 500 mA sink current, Note 1 | 5 | |
| Low Drive Source Current | ILO_SRC | 2 | A | Note 1 | 5 | ||
| Low Drive Sink Current | ILO_SINK | 3.5 | A | Note 1 | 5 | ||
| HIGHDR Turn-off Propagation Delay | tPDLH | 20 | 27 | 36 | ns | No Load, Note 1, Note 2 | 6 |
| LOWDR Turn-off Propagation Delay | tPDLL | 10 | 17 | 25 | ns | No Load, Note 1, Note 2 | 6 |
| HIGHDR Turn-on Propagation Delay | tPDHH | 20 | 27 | 36 | ns | No Load, Note 1, Note 2 | 6 |
| LOWDR Turn-on Propagation Delay | tPDHL | 10 | 17 | 25 | ns | No Load, Note 1, Note 2 | 6 |
| Thermal Resistance, 8L-SOIC junction-to-ambient | JA | 163 | °C/W | 6 | |||
| Thermal Resistance, 8L-SOIC junction-to-case | JC | 42 | °C/W | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Package: MF = Plastic Dual Flat, No Lead (3x3 DFN), 8-lead SN = Plastic Small Outline, (3.90 mm), 8-lead | 25 |
CAD (KiCad official)
- Symbol:
MCP14700-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mcp14700-e-etched.step/mcp14700-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp14700-e.step/mcp14700-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (28 pp, sha256
084e557d6c8178d6, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).