LAN9221I-ABZJ from Microchip Tech, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD33REG	power_in	+3.3V power supply for the internal +1.8V core regulator.
2	VDD18CORE	power_out	+1.8V output from the internal core regulator; must be connected together with pin 37 and each pin needs a 0.01uF decoupling capacitor, with a 4.7uF bulk capacitor (<2 Ohm ESR) in parallel on pin 2, and must not supply other external devices.
3	GPIO0/nLED1	bidirectional	General purpose I/O 0, programmable as push-pull output, open-drain output or Schmitt-triggered input, also multiplexed as nLED1 which is driven low at 100Mb operation.
4	GPIO1/nLED2	bidirectional	General purpose I/O 1, programmable as push-pull, open-drain or input, also multiplexed as nLED2 which is driven low when a valid link is detected and flashes for activity.
5	GPIO2/nLED3	bidirectional	General purpose I/O 2, programmable as push-pull, open-drain or input, also multiplexed as nLED3 which is driven low when the link operates in full-duplex mode.
6	A7	input	Bit 7 of the 7-bit host address port used to select internal CSRs and TX/RX FIFOs; ignored when FIFO_SEL is high.
7	A6	input	Bit 6 of the 7-bit host address port used to select internal CSRs and TX/RX FIFOs; ignored when FIFO_SEL is high.
8	A5	input	Bit 5 of the 7-bit host address port used to select internal CSRs and TX/RX FIFOs; ignored when FIFO_SEL is high.
9	A4	input	Bit 4 of the 7-bit host address port used to select internal CSRs and TX/RX FIFOs; ignored when FIFO_SEL is high.
10	A3	input	Bit 3 of the 7-bit host address port used to select internal CSRs and TX/RX FIFOs; ignored when FIFO_SEL is high.
11	A2	input	Host address bit 2 of the 7-bit address port used to select internal CSRs and TX/RX FIFOs.
12	A1	input	Host address bit 1 of the 7-bit address port used to select internal CSRs and TX/RX FIFOs.
13	FIFO_SEL	input	When driven high, all accesses to the device go to the RX or TX data FIFOs and the upper address inputs A[7:3] are ignored.
14	TEST	input	Reserved for internal test; must be connected to ground or pulled low with an external resistor when VDDVARIO is below 3.0V, and may be left unconnected at VDDVARIO = 3.3V.
15	nRD	input	Active-low strobe indicating a host read cycle.
16	nWR	input	Active-low strobe indicating a write cycle; qualified with nCS, it also wakes the device from a reduced power state.
17	nCS	input	Active-low chip select qualifying read and write operations; qualified with nWR it also wakes the device from a reduced power state.
18	VDDVARIO	power_in	Variable voltage I/O logic power supply pin, supporting I/O signalling from 1.8V to 3.3V.
19	D15	bidirectional	Host data bus bit 15 of the 16-bit bi-directional data port.
20	D14	bidirectional	Host data bus bit 14 of the 16-bit bi-directional data port.
21	D13	bidirectional	Host data bus bit 13 of the 16-bit bi-directional data port.
22	D12	bidirectional	Host data bus bit 12 of the 16-bit bi-directional data port.
23	D11	bidirectional	Host data bus bit 11 of the 16-bit bi-directional data port.
24	VDDVARIO	power_in	Variable voltage I/O logic power supply pin, supporting I/O signalling from 1.8V to 3.3V.
25	D10	bidirectional	Host data bus bit 10 of the 16-bit bi-directional data port.
26	D9	bidirectional	Host data bus bit 9 of the 16-bit bi-directional data port.
27	D8	bidirectional	Host data bus bit 8 of the 16-bit bi-directional data port.
28	D7	bidirectional	Host data bus bit 7 of the 16-bit bi-directional data port.
29	D6	bidirectional	Host data bus bit 6 of the 16-bit bi-directional data port.
30	VDDVARIO	power_in	Variable voltage I/O logic power supply pin, supporting I/O signalling from 1.8V to 3.3V.
31	D5	bidirectional	Host data bus bit 5 of the 16-bit bi-directional data port.
32	D4	bidirectional	Host data bus bit 4 of the 16-bit bi-directional data port.
33	D3	bidirectional	Host data bus bit 3 of the 16-bit bi-directional data port.
34	D2	bidirectional	Host data bus bit 2 of the 16-bit bi-directional data port.
35	D1	bidirectional	Host data bus bit 1 of the 16-bit bi-directional data port.
36	D0	bidirectional	Host data bus bit 0 of the 16-bit bi-directional data port.
37	VDD18CORE	power_out	+1.8V output from the internal core regulator; must be connected together with pin 2 and each pin needs a 0.01uF decoupling capacitor, and must not supply other external devices.
38	EEDIO/GPO3	bidirectional	Serial EEPROM data I/O (optional), or general purpose output GPO3, or a monitor of TX_EN/TX_CLK; it cannot function as a general purpose input.
39	EECS	output	Serial EEPROM chip select; deasserted when pins 38 or 40 are configured as GPO or monitor signals so the EEPROM is never accessed unintentionally.
40	EECLK/GPO4	bidirectional	Serial EEPROM clock, or general purpose output GPO4, or a monitor of RX_DV/RX_CLK; it must not be pulled low by an external resistor or driven low externally, and must be pulled up when VDDVARIO is below 3.0V.
41	PME	output	Wakeup indicator asserted when a wake event is detected, with programmable polarity and buffer type; asserting PME does not by itself wake the device.
42	nRESET	input	Active-low reset input that resets all logic and registers, pulled high by a weak internal pull-up, and must be reset on power-up.
43	IRQ	output	Programmable interrupt request with programmable polarity, source and buffer type, configurable as open-drain for sharing.
44	TPO-	output	Transmit negative output in normal connection; acts as receive negative input when HP Auto-MDIX detects or is set to a reversed connection.
45	TPO+	output	Transmit positive output in normal connection; acts as receive positive input when HP Auto-MDIX detects or is set to a reversed connection.
46	VDD33A	power_in	+3.3V analog power supply pin.
47	TPI-	input	Receive negative input in normal connection; acts as transmit negative output when HP Auto-MDIX reverses the connection.
48	TPI+	input	Receive positive input in normal connection; acts as transmit positive input when HP Auto-MDIX reverses the connection.
49	VDD33A	power_in	+3.3V analog power supply pin.
50	EXRES	input	PHY external bias resistor pin that must be connected to ground through a 12.4K ohm 1% resistor.
51	VDD33A	power_in	+3.3V analog power supply pin.
52	AMDIX_EN	input	Enables Auto-MDIX when pulled high or left unconnected and disables it when pulled low; must be pulled to a valid level by an external resistor when VDDVARIO is below 3.0V.
53	VDD18A	power_in	+1.8V analog power supply pin that must be connected externally to VDD18CORE.
54	XTAL2	output	External 25MHz crystal output; should be left unconnected when pin 55 is driven by a single-ended TTL oscillator.
55	XTAL1/CLKIN	input	External 25MHz crystal input, which can alternatively be driven by a single-ended TTL oscillator (CLKIN).
56	VDDVARIO	power_in	Variable voltage I/O logic power supply pin, supporting I/O signalling from 1.8V to 3.3V.
57	VSS	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-56-EP(8x8)
Category	Communication Interface Chip/UART/485/232
Pins	57

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDDVARIO, VDD33REG, VDD33A)		0		3.6	V	Note 7-1	125
Positive voltage on signal pins, with respect to ground				6	V	Note 7-2: does not apply to XTAL1/CLKIN, XTAL2, EXRES	125
Negative voltage on signal pins, with respect to ground		-0.5			V	Note 7-3: does not apply to EXRES	125
Positive voltage on XTAL1/CLKIN, with respect to ground				4.6	V		125
Positive voltage on XTAL2, with respect to ground				2.5	V		125
Storage Temperature		-65		150	°C		125
HBM ESD Performance		-5		5	kV	HBM; printed as +/-5kV	125
Ambient Operating Temperature in Still Air (TA), industrial version	TA	-40		85	°C	Note 7-4: -40°C to +85°C for industrial version	125
Supply Voltage (VDDVARIO)	VDDVARIO	1.62		3.6	V		125
Ambient Operating Temperature in Still Air (TA), industrial version	TA	-40		85	°C	Note 7-4: -40°C to +85°C for industrial version	125
Negative-Going Threshold, VIS input buffer	VILT	1.01	1.18	1.35	V	VDDVARIO=3.3V +/- 300mV; Schmitt Trigger	129
Positive-Going Threshold, VIS input buffer	VIHT	1.4	1.61	1.81	V	VDDVARIO=3.3V +/- 300mV; Schmitt Trigger	129
Schmitt Trigger Hysteresis (VIHT - VILT), VIS input buffer	VHYS	350	423	492	mV	VDDVARIO=3.3V +/- 300mV	129
Input Leakage, VIS input buffer	IIH	-10		10	uA	VDDVARIO=3.3V +/- 300mV; VIN = VSS or VDDVARIO; Note 7-9	129
Low Output Level, VO12 buffer	VOL			0.4	V	VDDVARIO=3.3V +/- 300mV; IOL = 12mA	129
Low Output Level, VOD12 buffer	VOL			0.4	V	VDDVARIO=3.3V +/- 300mV; IOL = 12mA	129
Low Output Level, VOD8 buffer	VOL			0.4	V	VDDVARIO=3.3V +/- 300mV; IOL = 8mA	129
Low Output Level, VO8 buffer	VOL			0.4	V	VDDVARIO=3.3V +/- 300mV; IOL = 8mA	129
Low Input Level, ICLK input buffer	VILCK	-0.3		0.5	V	VDDVARIO=3.3V +/- 300mV	129
High Input Level, ICLK input buffer	VIHCK	1.4		3.6	V	VDDVARIO=3.3V +/- 300mV	129
Negative-Going Threshold, VIS input buffer	VILT	0.78	0.94	1.1	V	VDDVARIO=2.5V +/- 10%; Schmitt Trigger	130
Positive-Going Threshold, VIS input buffer	VIHT	1.13	1.32	1.51	V	VDDVARIO=2.5V +/- 10%; Schmitt Trigger	130
Schmitt Trigger Hysteresis (VIHT - VILT), VIS input buffer	VHYS	304	384	472	mV	VDDVARIO=2.5V +/- 10%	130
Input Leakage, VIS input buffer	IIH	-10		10	uA	VDDVARIO=2.5V +/- 10%; VIN = VSS or VDDVARIO; Note 7-9	130
Low Output Level, VO12 buffer	VOL			0.4	V	VDDVARIO=2.5V +/- 10%; IOL = 9mA	130
Low Output Level, VOD12 buffer	VOL			0.4	V	VDDVARIO=2.5V +/- 10%; IOL = 9mA	130
Low Output Level, VOD8 buffer	VOL			0.4	V	VDDVARIO=2.5V +/- 10%; IOL = 6mA	130
Low Output Level, VO8 buffer	VOL			0.4	V	VDDVARIO=2.5V +/- 10%; IOL = 6mA	130
Low Input Level, ICLK input buffer	VILCK	-0.3		0.5	V	VDDVARIO=2.5V +/- 10%	130
High Input Level, ICLK input buffer	VIHCK	1.4		3.6	V	VDDVARIO=2.5V +/- 10%	130
Negative-Going Threshold, VIS input buffer	VILT	0.54	0.69	0.83	V	VDDVARIO=1.8V +/- 10%; Schmitt Trigger	131
Positive-Going Threshold, VIS input buffer	VIHT	0.878	1.06	1.24	V	VDDVARIO=1.8V +/- 10%; Schmitt Trigger	131
Schmitt Trigger Hysteresis (VIHT - VILT), VIS input buffer	VHYS	277	368	525	mV	VDDVARIO=1.8V +/- 10%	131
Input Leakage, VIS input buffer	IIH	-10		10	uA	VDDVARIO=1.8V +/- 10%; VIN = VSS or VDDVARIO; Note 7-9	131
Low Output Level, VO12 buffer	VOL			0.4	V	VDDVARIO=1.8V +/- 10%; IOL = 4mA	131
Low Output Level, VOD12 buffer	VOL			0.4	V	VDDVARIO=1.8V +/- 10%; IOL = 4mA	131
Low Output Level, VOD8 buffer	VOL			0.4	V	VDDVARIO=1.8V +/- 10%; IOL = 3mA	131
Low Output Level, VO8 buffer	VOL			0.4	V	VDDVARIO=1.8V +/- 10%; IOL = 3mA	131
Low Input Level, ICLK input buffer	VILCK	-0.3		0.5	V	VDDVARIO=1.8V +/- 10%	131
High Input Level, ICLK input buffer	VIHCK	1.4		3.6	V	VDDVARIO=1.8V +/- 10%	131
Variable Voltage Supply Current	VDDVARIO			12	mA	VDDVARIO=3.3V + 300MV; supply voltage 3.6V	128
+3.3V Regulator Supply Current	VDD33REG			85	mA	VDDVARIO=3.3V + 300MV; supply voltage 3.6V	128
+3.3V Analog Supply Current	VDD33A			48	mA	VDDVARIO=3.3V + 300MV; supply voltage 3.6V	128
Variable Voltage Supply Current	VDDVARIO			9	mA	VDDVARIO=2.5V + 10%; supply voltage 2.75V	128
Variable Voltage Supply Current	VDDVARIO			7	mA	VDDVARIO=1.8V + 10%; supply voltage 1.98V	128
Peak Differential Output Voltage High (100BASE-TX)	VPPH	950		1050	mVpk	Note 7-11	132
Peak Differential Output Voltage Low (100BASE-TX)	VPPL	-950		-1050	mVpk	Note 7-11	132
Signal Amplitude Symmetry (100BASE-TX)	VSS	98		102	%	Note 7-11	132
Signal Rise & Fall Time (100BASE-TX)	TRF	3		5	nS	Note 7-11	132
Duty Cycle Distortion (100BASE-TX)	DCD	35	50	65	%	Note 7-12	132
Transmitter Peak Differential Output Voltage (10BASE-T)	VOUT	2.2	2.5	2.8	V	Note 7-14	132
Receiver Differential Squelch Threshold (10BASE-T)	VDS	300	420	585	mV		132
Input Clock Duty Cycle (CLKIN)		40	50	60	%	25 MHz clock oscillator input	133
Frequency Tolerance @ 25°C (crystal)	Ftol	-50		50	PPM	Note 7-15	133
Equivalent Series Resistance (crystal)	R1			50	Ohm		133
Drive Level (crystal)	PW	300			uW		133
Power supply turn on time	tpon			50	ms	Power applied to all 3.3V supply pins simultaneously	122
Power supply turn off time	tpoff			500	ms	Power removed from all 3.3V supply pins simultaneously	122
+3.3V supply nominal voltage (VDD33REG, VDD33A)	VDD33REG, VDD33A		3.3		V	+3.3V +/-300mV	125

CAD (KiCad official)

Symbol: LAN9221I-ABZJ
Footprint: Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm
3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
3D model files: lan9221i-abzj-etched.step / lan9221i-abzj-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9221i-abzj.step / lan9221i-abzj.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (141 pp, sha256 e55ed0f7c6ba0abd, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LAN9221I-ABZJ

Verified LAN9221I-ABZJ

Verification log 1 record

3D Model

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Schematic Symbol

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