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Contents

README

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UCC27517

Texas Instruments · Low-side gate driver · SOT-23-5

Single-channel, high-speed low-side gate driver in a SOT-23-5 package, with symmetrical +/-4 A peak source and sink into a power MOSFET gate. It runs from a 4.5 to 18 V bias and takes a MCU/PWM logic signal on a matched pair of inputs (IN+ noninverting, IN- inverting) with TTL/CMOS thresholds independent of VDD, so you pick the polarity and use the other input as an enable. Internal UVLO holds OUT low for glitch-free power-up. The buffer between a controller and a big MOSFET when the pin can't drive the gate fast enough.

Pinout

Pin Name Type Function
1 VDD power_in Bias supply input. Recommended operating range 4.5 V to 18 V (12 V nominal). Bypass to GND with a low-ESR capacitor (e.g., 1 µF) placed close to the device. Internal UVLO holds OUT low outside the VDD operating range.
2 GND power_in Ground return. All device signals are referenced to this pin. Provide a low-inductance path back to the source of the driven power MOSFET.
3 IN+ input Noninverting driver input. When used in inverting configuration, tie IN+ to VDD to enable the output; OUT is held LOW if IN+ is unbiased or floating. TTL/CMOS-compatible thresholds (V_IH typ 2.2 V, V_IL typ 1.2 V) independent of VDD, with ~1 V hysteresis. Absolute max on input pins is 20 V, not restricted by VDD.
4 IN- input Inverting driver input. When used in noninverting configuration, tie IN- to GND to enable the output; OUT is held LOW if IN- is unbiased or floating. Shares the same TTL/CMOS-compatible thresholds and hysteresis as IN+. May be used as an enable/disable pin when the driver is configured single-input.
5 OUT output Gate-drive sourcing/sinking current output. Symmetrical ±4-A peak drive into a capacitive load (rail-to-rail). Typical R_OH ≈ 5 Ω (P-channel pullup) and R_OL ≈ 0.5 Ω (pulldown) at VDD = 12 V. Held LOW during VDD UVLO to guarantee glitch-free power-up/down.

Key specifications

Parameter Value
Type Single-channel low-side gate driver
Peak drive +/-4 A (symmetrical, rail-to-rail)
Bias voltage (VDD) 4.5-18 V
Inputs IN+ / IN- (TTL/CMOS, VDD-independent thresholds)
Pull-up / pull-down ROH ~5 ohm / ROL ~0.5 ohm @ 12 V
Protection UVLO holds OUT low
Package SOT-23-5
Body (L×W×H) 2.9 × 1.6 × 1.1 mm

Ordering variants

Same part, different packaging or reel option.

  • UCC27517DBVR (SOT-23-5, tape & reel)

CAD (KiCad official)

  • Symbol: UCC27517 (Adom-authored grouped symbol via adom-symbol; not in KiCad libs)
  • Footprint: Package_TO_SOT_SMD:SOT-23-5
  • 3D model: SOT-23-5 (KiCad packages3D)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 6b7b8c088746010d, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude) — every pin and dimension is cited to a datasheet page; refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF