component
MIC27600YJL-TR
Public Made by Adomby adom
Microchip Tech DC-DC Converters, QFN-28(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMIC27600YJL-TR
Microchip Tech · DC-DC Converters · QFN-28(5x6)
MIC27600YJL-TR from Microchip Tech, in a QFN-28(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connect pin. |
| 2 | PGND | power_in | Power ground for the buck power stage, connected to the low-side MOSFET sources and the negative terminals of input and output capacitors, and kept separate from the signal ground loop. |
| 3 | NC | unconnected | No connect pin. |
| 4 | SW | output | Switch node connecting the high-side MOSFET source and the low-side MOSFET drain. |
| 5 | PGND | power_in | Power ground for the buck power stage, connected to the low-side MOSFET sources and the negative terminals of input and output capacitors, and kept separate from the signal ground loop. |
| 6 | PGND | power_in | Power ground for the buck power stage, connected to the low-side MOSFET sources and the negative terminals of input and output capacitors, and kept separate from the signal ground loop. |
| 7 | PGND | power_in | Power ground for the buck power stage, connected to the low-side MOSFET sources and the negative terminals of input and output capacitors, and kept separate from the signal ground loop. |
| 8 | PGND | power_in | Power ground for the buck power stage, connected to the low-side MOSFET sources and the negative terminals of input and output capacitors, and kept separate from the signal ground loop. |
| 9 | SW | output | Switch node connecting the high-side MOSFET source and the low-side MOSFET drain. |
| 10 | SW | output | Switch node connecting the high-side MOSFET source and the low-side MOSFET drain. |
| 11 | SW | output | Switch node connecting the high-side MOSFET source and the low-side MOSFET drain. |
| 12 | SW | output | Switch node connecting the high-side MOSFET source and the low-side MOSFET drain. |
| 13 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 14 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 15 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 16 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 17 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 18 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 19 | PVIN | power_in | High-side MOSFET drain input operating from 4.5V to 36V, with input capacitors between PVIN and PGND required and kept short. |
| 20 | BST | output | Bootstrapped supply output for the high-side N-channel MOSFET driver, fed through a Schottky diode from VDD and with a 0.1µF boost capacitor between BST and SW. |
| 21 | PGND | power_in | Power ground for the buck power stage, connected to the low-side MOSFET sources and the negative terminals of input and output capacitors, and kept separate from the signal ground loop. |
| 22 | CS | input | Current sense input and high-current output driver return connected directly to the switch node, sensing current across the low-side MOSFET during OFF-time and to be routed away from sensitive nodes. |
| 23 | VIN | power_in | Power supply voltage input that requires a bypass capacitor to SGND. |
| 24 | EN | input | CMOS-compatible enable: logic high or floating enables the device, logic low shuts it down, and EN must not be pulled above the VDD supply. |
| 25 | FB | input | Feedback input to the transconductance amplifier, regulated to 0.8V, with a resistor divider from the output setting the output voltage. |
| 26 | SGND | power_in | Signal ground that must be connected directly to the ground planes and must not be routed to the PGND pad on the top layer. |
| 27 | VDD | power_in | Bias supply for the internal reference and control sections, operating from 4.5V to 5.5V, with a 2.2µF ceramic capacitor to PGND placed next to the IC and VDD powered up at the same time as or after VIN. |
| 28 | NC | unconnected | No connect pin. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QFN-28(5x6) |
| Category | Power Management (PMIC) |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Voltage Range (VIN, PVIN) | VIN, PVIN | 4.5 | 36 | V | 4 | ||
| Operating Bias Voltage (VDD) | VDD | 4.5 | 5 | 5.5 | V | 4 | |
| Under-Voltage Lockout Trip Level | 2.4 | 2.7 | 3.2 | V | VDD Rising | 4 | |
| Feedback Reference Voltage | 0.792 | 0.8 | 0.808 | V | 0°C ≤ TJ ≤ 85°C (±1.0%) | 4 | |
| Feedback Reference Voltage | 0.788 | 0.8 | 0.812 | V | −40°C ≤ TJ ≤ +125°C (±1.5%) | 4 | |
| Output Voltage Range | 0.8 | 5.5 | V | 3.0V ≤ VHSD ≤ 28V | 4 | ||
| Output Voltage Range | 0.8 | 3.6 | V | 3.0V ≤ VHSD ≤ 36V | 4 | ||
| Quiescent Supply Current | 1.4 | 3 | mA | VFB = 1.5V | 4 | ||
| Shutdown Supply Current | 0.7 | 2 | mA | VDD = VBST = 5.5V, VIN = 36V, SW unconnected, VEN = 0V | 4 | ||
| Switching Frequency | 225 | 300 | 375 | kHz | 5 | ||
| Current-Limit Threshold | 7.7 | 15 | A | VFB = 0.8V | 5 | ||
| PVIN to PGND | -0.3 | 38 | V | 4 | |||
| VIN to PGND | -0.3 | V | 4 | ||||
| VDD to PGND | -0.3 | 6 | V | 4 | |||
| VSW, VCS to PGND | VSW, VCS | -0.3 | V | 4 | |||
| VBST to VSW | -0.3 | 6 | V | 4 | |||
| VBST to PGND | -0.3 | 44 | V | 4 | |||
| VEN to PGND | VEN | -0.3 | V | 4 | |||
| VFB to PGND | VFB | -0.3 | V | 4 | |||
| PGND to SGND | -0.3 | 0.3 | V | 4 | |||
| Junction Temperature | 150 | °C | 4 | ||||
| Storage Temperature | TS | -65 | 150 | °C | 4 | ||
| Lead Temperature | 260 | °C | soldering, 10sec | 4 | |||
| Supply Voltage (PVIN, VIN) | PVIN, VIN | 4.5 | 36 | V | 4 | ||
| Bias Voltage (VDD) | VDD | 4.5 | 5.5 | V | 4 | ||
| Enable Input (VEN) | VEN | 0 | V | 4 | |||
| Junction Temperature (TJ) | TJ | -40 | 125 | °C | 4 | ||
| Package Thermal Resistance (5mm x 6mm MLF) θJA | θJA | 36 | °C/W | 4 | |||
| UVLO Hysteresis | 50 | mV | 4 | ||||
| Load Regulation | 0.2 | % | IOUT = 0A to 7A | 4 | |||
| Line Regulation | 0.1 | % | VIN = (VOUT + 3.0V) to 36V | 4 | |||
| FB Bias Current | 5 | nA | VFB = 0.8V | 4 | |||
| EN Bias Current | 50 | µA | VEN = 0V | 4 | |||
| Maximum Duty Cycle | 87 | % | VFB = 0V | 5 | |||
| Minimum Duty Cycle | 0 | % | VFB > 0.8V | 5 | |||
| Minimum Off-time | 360 | ns | 5 | ||||
| Soft-Start time | 6 | ms | 5 | ||||
| Short-Circuit Current | 6 | A | VFB = 0V | 5 | |||
| Top-MOSFET RDS(ON) | RDS(ON) | 25 | mΩ | ISW = 1A | 5 | ||
| Bottom-MOSFET RDS(ON) | RDS(ON) | 10 | mΩ | ISW = 1A | 5 | ||
| SW Leakage Current | 60 | µA | VIN = 36V, VSW = 36V, VEN = 0V, VBST = 41V | 5 | |||
| VIN Leakage Current | 25 | µA | VIN = 36V, VSW = 0V, VEN = 0V, VBST = 41V | 5 | |||
| Over-Temperature Shutdown | 155 | °C | TJ Rising | 5 | |||
| Over-Temperature Shutdown Hysteresis | 10 | °C | 5 |
CAD (KiCad official)
- Symbol:
MIC27600YJL-TR - Footprint:
Package_DFN_QFN:QFN-28-1EP_5x6mm_P0.5mm_EP3.65x4.65mm - 3D model: QFN-28(5x6) (KiCad packages3D, STEP)
- 3D model files:
mic27600yjl-tr-etched.step/mic27600yjl-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic27600yjl-tr.step/mic27600yjl-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (28 pp, sha256
3391f4d17278f339, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).