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MSPM0G3506SRHBR

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TI(德州仪器) , VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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MSPM0G3506SRHBR

TI(德州仪器) · IC · VQFN-32(5x5)

MSPM0G3506SRHBR from TI(德州仪器), in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional 5V-tolerant open-drain GPIO with wake from SHUTDOWN; UART0_TX, I2C0_SDA, TIMA0_C0, FCC_IN, default BSL I2C data (BSLSDA); needs a pullup to output high.
2 PA1 bidirectional 5V-tolerant open-drain GPIO with wake from SHUTDOWN; UART0_RX, I2C0_SCL, TIMA0_C1, default BSL I2C clock (BSLSCL); needs a pullup to output high.
3 NRST input Active-low reset input; must be pulled high to VDD for the device to start.
4 VDD power_in Power supply, 1.62V to 3.6V, with 10uF capacitor to VSS recommended.
5 VSS power_in Ground supply.
6 PA2 bidirectional Standard-drive GPIO or ROSC external resistor pin (100k to VSS) for SYSOSC accuracy; SPI0_CS0, TIMG7_C1.
7 PA3 bidirectional Standard-drive GPIO or LFXIN low-frequency crystal input; also SPI0_CS1, UART2_CTS, COMP1_OUT, I2C1_SDA.
8 PA4 bidirectional Standard-drive GPIO or LFXOUT crystal output / LFCLK_IN; also SPI0_POCI, UART2_RTS, I2C1_SCL.
9 PA5 bidirectional Standard-drive GPIO or HFXIN high-frequency crystal input; also SPI0_PICO, FCC_IN.
10 PA6 bidirectional Standard-drive GPIO or HFXOUT crystal output / HFCLK_IN; also SPI0_SCK, TIMG0_C1.
11 PA7 bidirectional Standard-drive GPIO with COMP0_OUT, CLK_OUT, TIMG8_C0 and TIMA0 functions.
12 PA8 bidirectional Standard-drive GPIO with UART1_TX, SPI0_CS0, UART0_RTS and TIMA functions.
13 PA9 bidirectional High-speed GPIO with UART1_RX, SPI0_PICO, UART0_CTS, RTC_OUT and CLK_OUT functions.
14 PA10 bidirectional High-drive GPIO with wake from SHUTDOWN; UART0_TX, SPI0_POCI, I2C0_SDA, CLK_OUT, default BSL UART transmit (BSLTX).
15 PA11 bidirectional High-drive GPIO with wake from SHUTDOWN; UART0_RX, SPI0_SCK, I2C0_SCL, COMP0_OUT, default BSL UART receive (BSLRX).
16 PA12 bidirectional High-speed GPIO with UART3_CTS, SPI0_SCK, CAN_TX and FCC_IN functions.
17 PA13 bidirectional High-speed GPIO with COMP0_IN2- analog input, UART3_RTS/RX, SPI0_POCI and CAN_RX functions.
18 PA14 bidirectional High-speed GPIO with ADC0 channel A0_12 and COMP0_IN2+ analog inputs, UART0_CTS, SPI0_PICO, UART3_TX, CLK_OUT.
19 PA15 bidirectional Standard-drive GPIO with ADC1 input A1_0, DAC_OUT, OPA0_IN2+, OPA1_IN2+, COMP0_IN3+, COMP1_IN3+ analog functions.
20 PA16 bidirectional Standard-drive GPIO with ADC1 input A1_1 and OPA1_OUT analog output; also COMP2_OUT, SPI1_POCI, I2C1_SDA.
21 PA17 bidirectional Standard GPIO with wake from SHUTDOWN; A1_2, OPA1_IN1-, COMP0_IN1- analog; UART1_TX, SPI1_SCK, I2C1_SCL.
22 PA18 bidirectional Standard GPIO with wake from SHUTDOWN; A1_3, OPA1_IN1+, COMP0_IN1+, GPAMP_IN- analog; default BSL_invoke input; UART1_RX, SPI1_PICO.
23 PA19 bidirectional High-speed GPIO; SWDIO serial wire debug data input/output.
24 PA20 input Standard-drive GPIO; SWCLK serial wire debug clock input.
25 PA21 bidirectional Standard-drive GPIO with ADC1 input A1_7, COMP2_IN1- and VREF- reference ground; no injection current allowed on this pin.
26 PA22 bidirectional Standard-drive GPIO with ADC0 input A0_7, GPAMP_OUT and OPA0_OUT analog; UART2_RX, CLK_OUT.
27 PA23 bidirectional Standard-drive GPIO with COMP1_IN1- input and VREF+ external reference input / internal reference output.
28 PA24 bidirectional Standard-drive GPIO with ADC0 input A0_3 and OPA0_IN1- analog; UART2_RX, SPI0_CS2.
29 PA25 bidirectional Standard-drive GPIO with ADC0 input A0_2 and OPA0_IN1+ analog; UART3_RX, SPI1_CS3.
30 PA26 bidirectional Standard-drive GPIO with A0_1, COMP0_IN0+, OPA0_IN0+, GPAMP_IN+ analog; UART3_TX, SPI1_CS0, CAN_TX.
31 PA27 bidirectional Standard-drive GPIO with A0_0, COMP0_IN0-, OPA0_IN0- analog; RTC_OUT, SPI1_CS1, CAN_RX.
32 VCORE power_out Regulated core supply output; connect only a 470nF (0.47uF) capacitor to VSS and no other load or supply.
33 PAD power_in Exposed thermal pad; TI recommends connection to VSS.

Key specifications

Parameter Value
Manufacturer TI(德州仪器)
Package VQFN-32(5x5)
Category
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD 1.62 3.6 V 25
Ambient temperature, S version TA -40 125 °C 25
Max junction temperature, S version TJ 130 °C 25
Capacitor between VDD and VSS CVDD 10 uF 25
Capacitor between VCORE and VSS CVCORE 470 nF 25
MCLK frequency with 2 flash wait states fMCLK 80 MHz MCLK, CPUCLK frequency with 2 flash wait states 26
ULPCLK frequency fULPCLK 40 MHz 26
Supply voltage VDD -0.3 4.1 V At VDD pin 25
Input voltage 5-V tolerant open-drain pins VI -0.3 5.5 V Applied to any 5-V tolerant open-drain pins 25
Junction temperature TJ -40 130 °C 25
Storage temperature Tstg -40 150 °C 25
ESD HBM V(ESD) -2000 2000 V HBM, all pins 25
ESD CDM V(ESD) -500 500 V CDM, all pins 25
Junction-to-ambient thermal resistance RθJA 32.1 °C/W VQFN-32 (RHB) 26
Junction-to-case (top) thermal resistance RθJC(top) 23.6 °C/W VQFN-32 (RHB) 26
Junction-to-board thermal resistance RθJB 13 °C/W VQFN-32 (RHB) 26
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.3 °C/W VQFN-32 (RHB) 26
Supply current in SHUTDOWN mode IDDSHDN 40 80 nA VDD 3.3V, -40°C 29
Power-on reset voltage level rising VPOR+ 0.95 1.3 1.59 V Rising 29
Power-on reset voltage level falling VPOR- 0.9 1.25 1.54 V Falling 29
Brown-out reset level 0 rising VBOR0+ 1.56 1.59 1.62 V Rising (1) 30
Flash program/erase supply voltage VDDPGM/ERASE 1.62 3.6 V 30
SYSOSC accuracy FCL disabled 32MHz fSYSOSC -2.6 1.8 % SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40 ℃ ≤ Ta ≤ 125 ℃ 33
LFOSC accuracy -5 5 % -40 ℃ ≤ Ta ≤ 125 ℃ 33
VREF output voltage VREF 1.38 1.4 1.42 V BUFCONFIG = 1 41
VREF output voltage VREF 2.46 2.5 2.54 V BUFCONFIG = 0 41
Comparator input offset voltage Voffset -20 20 mV 42
ADC INL EI -2 2 LSB External reference 40
ADC offset error EO -5 5 mV Internal or External reference 40

CAD (KiCad official)

  • Symbol: MSPM0G3506SRHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: mspm0g3506srhbr-etched.step / mspm0g3506srhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); mspm0g3506srhbr.step / mspm0g3506srhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TI(德州仪器) datasheet (120 pp, sha256 0cba2418fd28709c, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF