component
MCP4922T-E
Public Made by Adomby adom
Microchip Tech Digital To Analog Converters (DAC), TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMCP4922T-E
Microchip Tech · Digital To Analog Converters (DAC) · TSSOP-14
MCP4922T-E from Microchip Tech, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Positive supply voltage input, which can range from 2.7V to 5.5V relative to VSS; a 0.1 µF ceramic bypass capacitor with a 10 µF tantalum in parallel is recommended. |
| 2 | NC | unconnected | No connection. |
| 3 | CS | input | Chip Select input that requires an active low signal to enable serial clock and data functions. |
| 4 | SCK | input | SPI compatible serial clock input. |
| 5 | SDI | input | SPI compatible serial data input. |
| 6 | NC | unconnected | No connection. |
| 7 | NC | unconnected | No connection. |
| 8 | LDAC | input | Latch DAC synchronization input; when low, VOUTA and VOUTB are updated simultaneously from their input registers, and it may be tied low (VSS) so updates occur on the rising edge of CS. |
| 9 | SHDN | input | Hardware shutdown input; when low, both DAC channels are shut down and DAC output is not available. |
| 10 | VOUTB | output | DAC B output, which the output amplifier can drive over a range of VSS to VDD. |
| 11 | VREFB | input | DAC B reference voltage input, with a range of VSS to VDD that may be tied to VDD. |
| 12 | VSS | power_in | Ground reference point for all circuitry on the device; the analog ground pin and current return path, to be connected through a low-impedance path to a ground plane. |
| 13 | VREFA | input | DAC A reference voltage input, with a range of VSS to VDD that may be tied to VDD. |
| 14 | VOUTA | output | DAC A output, which the output amplifier can drive over a range of VSS to VDD. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Voltage | VDD | 2.7 | 5.5 | V | 3 | ||
| Operating Current | IDD | 350 | 700 | µA | VDD = 5V; VREF unbuffered, digital inputs grounded, VOUT unloaded, Code = 000h | 3 | |
| Operating Current | IDD | 250 | 500 | µA | VDD = 3V; VREF unbuffered, digital inputs grounded, VOUT unloaded, Code = 000h | 3 | |
| Hardware Shutdown Current | ISHDN | 0.3 | 2 | µA | Power-on Reset circuit turned off | 3 | |
| Software Shutdown Current | ISHDN_SW | 3.3 | 6 | µA | Power-on Reset circuit stays on | 3 | |
| Resolution (MCP4922) | n | 12 | Bits | MCP4922 | 3 | ||
| INL Error (MCP4922) | INL | -12 | 2 | 12 | LSb | MCP4922 | 3 |
| DNL (MCP4922) | DNL | -0.75 | 0.2 | 0.75 | LSb | MCP4922; guaranteed monotonic by design over all codes (Note 1) | 3 |
| Offset Error | VOS | 0.02 | 1 | % of FSR | Code = 0x000h | 3 | |
| Gain Error | gE | -0.1 | 1 | % of FSR | Code = 0xFFFh, not including offset error | 4 | |
| Input Range - Buffered Mode (VREF) | VREF | 0.04 | V | Buffered mode (Note 2); printed max is VDD, 0.040 V, not numeric | 4 | ||
| Input Range - Unbuffered Mode (VREF) | VREF | 0 | V | Unbuffered mode; printed max is VDD, not numeric | 4 | ||
| Short Circuit Current | ISC | 15 | 24 | mA | 4 | ||
| Input Leakage Current | ILEAKAGE | -1 | 1 | µA | SHDN = LDAC = CS = SDI = SCK + VREF = VDD or VSS | 7 | |
| Clock Frequency | FCLK | 20 | MHz | TA = +25°C (Note 1) | 7 | ||
| Clock High Time | tHI | 15 | ns | Note 1 | 7 | ||
| Clock Low Time | tLO | 15 | ns | Note 1 | 7 | ||
| CS Fall to First Rising CLK Edge | tCSSR | 40 | ns | Applies only when CS falls with CLK high (Note 1) | 7 | ||
| Data Input Setup Time | tSU | 15 | ns | Note 1 | 7 | ||
| Data Input Hold Time | tHD | 10 | ns | Note 1 | 7 | ||
| SCK Rise to CS Rise Hold Time | tCHS | 15 | ns | Note 1 | 7 | ||
| CS High Time | tCSH | 15 | ns | Note 1 | 7 | ||
| LDAC Pulse Width | tLD | 100 | ns | Note 1 | 7 | ||
| LDAC Setup Time | tLS | 40 | ns | Note 1 | 7 | ||
| SCK Idle Time before CS Fall | tIDLE | 40 | ns | Note 1 | 7 | ||
| Specified Temperature Range | TA | -40 | 125 | °C | 8 | ||
| Operating Temperature Range | TA | -40 | 125 | °C | Note 1: must not cause TJ to exceed 150°C | 8 | |
| Storage Temperature Range | TA | -65 | 150 | °C | 8 | ||
| Supply Voltage (VDD) Absolute Maximum | VDD | 6.5 | V | 3 | |||
| Voltage on All Inputs and Outputs | -0.3 | V | w.r.t. VSS; printed upper limit is VDD + 0.3V, not numeric | 3 | |||
| Current at Input Pins | -2 | 2 | mA | 3 | |||
| Current at Supply Pins | -50 | 50 | mA | 3 | |||
| Current at Output Pins | -25 | 25 | mA | 3 | |||
| Ambient Temperature with Power Applied | -55 | 125 | °C | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 3 | |||
| Operating Voltage (extended temperature table) | VDD | 2.7 | 5.5 | V | Extended temperature table (typ at +125°C) | 5 | |
| INL Error (MCP4922, extended temperature) | INL | -4 | 4 | LSb | MCP4922; printed ±4 LSb; extended temperature table | 5 | |
| DNL (MCP4922, extended temperature) | DNL | -0.25 | 0.25 | LSb | MCP4922; printed ±0.25 LSb; Note 1; extended temperature table | 5 | |
| Offset Error (extended temperature) | VOS | -0.02 | 0.02 | % of FSR | Code 0x000h; printed ±0.02% of FSR; extended temperature table | 5 | |
| Input Range - Unbuffered Mode (VREF, extended temperature) | VREF | 0 | V | Unbuffered mode; printed max is VDD, not numeric; extended temperature table | 5 | ||
| Thermal Resistance, 14L-TSSOP | JA | 100 | °C/W | 14L-TSSOP package | 8 |
CAD (KiCad official)
- Symbol:
MCP4922T-E - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
mcp4922t-e-etched.step/mcp4922t-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mcp4922t-e.step/mcp4922t-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (48 pp, sha256
8c507a2bce321888, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).