component
TPS65265RHBT
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65265RHBT
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65265RHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | V7V | power_out | Internal LDO output for the gate driver and internal controller; connect a 10-µF capacitor from this pin to power ground. |
| 2 | PGOOD | output | Open-drain output that asserts low if any buck output is outside its regulation range due to thermal shutdown, over-current, under-voltage or ENx shutdown. |
| 3 | EN1 | input | Enable input for buck1; float to enable, and a resistor divider can set the buck1 input UVLO. |
| 4 | EN2 | input | Enable input for buck2; float to enable, and a resistor divider can set the buck2 input UVLO. |
| 5 | EN3 | input | Enable input for buck3; float to enable, and a resistor divider can set the buck3 input UVLO. |
| 6 | FB2 | input | Kelvin-sensing feedback input for the buck2 output voltage; connect to the buck2 resistor divider. |
| 7 | COMP2 | passive | Error amplifier output and loop compensation pin for buck2; connect a series resistor and capacitor to compensate the peak current mode loop. |
| 8 | MODE | input | When floating, Buck1/2/3 are enabled separately by EN1/EN2/EN3; when tied HIGH or GND, an automatic power-up/power-down sequence follows the EN1, EN2 and EN3 states. |
| 9 | BST2 | power_out | Bootstrap supply for the buck2 high-side gate driver; connect a capacitor (recommended 47 nF) from BST2 to LX2. |
| 10 | PGND2 | power_in | Power ground for buck2; connect as close as practical to the negative terminal of the PVIN2 input ceramic capacitor. |
| 11 | LX2 | output | Buck2 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN2 voltage. |
| 12 | PVIN2 | power_in | Input supply for buck2; connect as close as practical to the positive terminal of an input ceramic capacitor (suggested 10 µF). |
| 13 | PVIN3 | power_in | Input supply for buck3; connect as close as practical to the positive terminal of an input ceramic capacitor (suggested 10 µF). |
| 14 | LX3 | output | Buck3 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN3 voltage. |
| 15 | PGND3 | power_in | Power ground for buck3; connect as close as practical to the negative terminal of the PVIN3 input ceramic capacitor. |
| 16 | BST3 | power_out | Bootstrap supply for the buck3 high-side gate driver; connect a capacitor (recommended 47 nF) from BST3 to LX3. |
| 17 | SEQ_DLY | passive | Sets the delay between bucks in automatic power sequencing mode; connect an external capacitor to set the interval delay time. |
| 18 | COMP3 | passive | Error amplifier output and loop compensation pin for buck3; connect a series resistor and capacitor to compensate the peak current mode loop. |
| 19 | FB3 | input | Kelvin-sensing feedback input for the buck3 output voltage; connect to the buck3 resistor divider. |
| 20 | ROSC | passive | Oscillator frequency programming pin; connect an external resistor to set the switching frequency. |
| 21 | AGND | power_in | Analog ground common to the buck controllers and other analog circuits. |
| 22 | FB1 | input | Kelvin-sensing feedback input for the buck1 output voltage; connect to the buck1 resistor divider. |
| 23 | COMP1 | passive | Error amplifier output and loop compensation pin for buck1; connect a series resistor and capacitor to compensate the peak current mode loop. |
| 24 | PG_DLY | passive | PGOOD delay programming pin; connect an external capacitor to set the PGOOD delay time. |
| 25 | BST1 | power_out | Bootstrap supply for the buck1 high-side gate driver; connect a capacitor (recommended 47 nF) from BST1 to LX1. |
| 26 | PGND1 | power_in | Power ground for buck1; connect as close as practical to the negative terminal of the PVIN1 input ceramic capacitor. |
| 27 | PGND1 | power_in | Power ground for buck1; connect as close as practical to the negative terminal of the PVIN1 input ceramic capacitor. |
| 28 | LX1 | output | Buck1 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN1 voltage. |
| 29 | LX1 | output | Buck1 switching node to the inductor and bootstrap capacitor; swings from a diode drop below ground up to the PVIN1 voltage. |
| 30 | PVIN1 | power_in | Input supply for buck1; connect as close as practical to the positive terminal of an input ceramic capacitor (suggested 22 µF). |
| 31 | PVIN1 | power_in | Input supply for buck1; connect as close as practical to the positive terminal of an input ceramic capacitor (suggested 22 µF). |
| 32 | PSM | input | Tie HIGH or leave floating for pulse-skip mode (PSM); tie to GND for forced continuous current mode (FCCM). |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback reference voltage tolerance | -1.33 | 1.33 | % | 1 | |||
| Input voltage range (absolute max) | PVIN1, PVIN2, PVIN3, PGOOD | -0.3 | 20 | V | 5 | ||
| LX1, LX2, LX3 voltage | -1 | 19 | V | 5 | |||
| LX1, LX2, LX3 voltage transient | -1 | 21 | V | maximum withstand voltage transient <10 ns | 5 | ||
| BST1, BST2, BST3 voltage | -0.3 | 7 | V | referenced to LX1, LX2, LX3 pins, respectively | 5 | ||
| EN1, EN2, EN3, V7V, MODE, PSM voltage | -0.3 | 7 | V | 5 | |||
| FB1, FB2, FB3, COMP1, COMP2, COMP3, ROSC, SEQ_DLY, PG_DLY voltage | -0.3 | 3.6 | V | 5 | |||
| AGND, PGND1, PGND2, PGND3 voltage | -0.3 | 0.3 | V | 5 | |||
| Operating junction temperature | TJ | -40 | 150 | °C | 5 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 5 | ||
| ESD human-body model | V(ESD) | -2000 | 2000 | V | HBM, per ANSI/ESDA/JEDEC JS-001 | 5 | |
| ESD charged-device model | V(ESD) | -1000 | 1000 | V | CDM, per JEDEC JESD22-C101 | 5 | |
| Input voltage range (recommended) | PVIN1, PVIN2, PVIN3 | 4.5 | 17 | V | 5 | ||
| LX1, LX2, LX3 voltage (recommended) | -0.8 | 19 | V | Maximum withstand voltage transient <10 ns | 5 | ||
| BST1, BST2, BST3 voltage (recommended) | -0.1 | 6.8 | V | referenced to LX1, LX2, LX3 pins respectively | 5 | ||
| EN1, EN2, EN3, V7V, MODE, PSM voltage (recommended) | -0.1 | 6.3 | V | 5 | |||
| FB1, FB2, FB3, COMP1, COMP2, COMP3, ROSC, SEQ_DLY, PG_DLY voltage (recommended) | -0.1 | 3.3 | V | 5 | |||
| Operating junction temperature (recommended) | TJ | -40 | 125 | °C | 5 | ||
| Input voltage range | VIN | 4.5 | 17 | V | 7 | ||
| UVLO rising threshold | 3.6 | 3.8 | 4 | V | VIN rising | 7 | |
| UVLO falling threshold | 3 | 3.2 | 3.4 | V | VIN falling | 7 | |
| Shutdown supply current | IDDSDN | 9 | 11.5 | 14 | µA | PVIN = 12 V, EN1 = EN2 = EN3 = MODE = 0 V | 7 |
| Input quiescent current without buck1/2/3 switching | IDDQ_NSW | 550 | 680 | 800 | µA | EN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V | 7 |
| Input quiescent current, buck1 only switching disabled | IDDQ_NSW1 | 280 | 350 | 425 | µA | EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V | 7 |
| Input quiescent current, buck2 only switching disabled | IDDQ_NSW2 | 280 | 350 | 425 | µA | EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8 V | 7 |
| Input quiescent current, buck3 only switching disabled | IDDQ_NSW3 | 280 | 350 | 425 | µA | EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V | 7 |
| V7V LDO output voltage | V7V | 5.9 | 6.1 | 6.3 | V | PVIN1 = 12 V, V7V load current = 0 A | 7 |
| V7V LDO current limit | IOCP_V7V | 110 | 177 | 235 | mA | 7 | |
| Feedback voltage | VFB | 0.592 | 0.6 | 0.608 | V | VCOMP = 1.2 V | 7 |
| EN1/2/3 high-level input voltage | VENXH | 1.08 | 1.15 | 1.22 | V | 7 | |
| EN1/2/3 low-level input voltage | VENXL | 1.06 | 1.12 | 1.17 | V | 7 | |
| EN1/2/3 pullup current | IENX1 | 2.3 | 2.9 | 3.4 | µA | ENx = 1 V | 7 |
| EN1/2/3 pullup current | IENX2 | 5.1 | 6 | 6.8 | µA | ENx = 1.5 V | 7 |
| Error amplifier transconductance | Gm_EA | 174 | 350 | 530 | µS | –2 µA < ICOMPX < 2 µA | 7 |
| Buck1 peak inductor current limit | ILIMIT1 | 6 | 8 | 9.6 | A | 7 | |
| Buck1 low-side source current limit | ILIMITSOURCE1 | 5.3 | 7.7 | 10 | A | 7 | |
| Buck2 peak inductor current limit | ILIMIT2 | 3.85 | 5.2 | 6.65 | A | 7 | |
| Buck2 low-side source current limit | ILIMITSOURCE2 | 3 | 4.8 | 5.5 | A | 7 | |
| Buck3 peak inductor current limit | ILIMIT3 | 2.6 | 3.6 | 4.45 | A | 7 | |
| Buck3 low-side source current limit | ILIMITSOURCE3 | 2.6 | 3.7 | 4.6 | A | 7 | |
| MODE high-level input voltage | VMODE_H | 2.4 | 2.6 | 2.8 | V | 8 | |
| MODE low-level input voltage | VMODE_L | 0.11 | 0.16 | 0.23 | V | 8 | |
| PG_DLY threshold | VPG_DLYTH | 1.4 | 1.5 | 1.6 | V | 8 | |
| PG_DLY pullup current | IPG_DLY | 2 | 3 | 4.1 | µA | PG_DLY = 0.5 V | 8 |
| SEQ_DLY threshold 1 | VSEQ_DLYTH1 | 0.7 | 0.75 | 0.8 | V | 8 | |
| SEQ_DLY threshold 2 | VSEQ_DLYTH2 | 1.4 | 1.5 | 1.58 | V | 8 | |
| SEQ_DLY pullup current | ISEQ_DLY | 2 | 3 | 4.1 | µA | SEQ_DLY = 0.5 V | 8 |
| PSM high-level input voltage | VPSMH | 1.3 | 1.4 | 1.55 | V | 8 | |
| PSM low-level input voltage | VPSML | 1 | 1.1 | 1.2 | V | 8 | |
| Switching frequency | FSW | 580 | 610 | 640 | kHz | ROSC = 82.5 kΩ | 8 |
| Switching frequency range | FSW_range | 250 | 2300 | kHz | 8 | ||
| Clock sync minimum pulse width | tSYNC_w | 80 | ns | 8 | |||
| Junction-to-ambient thermal resistance | RθJA | 32 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 24.2 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 6.4 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ψJT | 0.2 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ψJB | 6.4 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1.3 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
TPS65265RHBT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65265rhbt-etched.step/tps65265rhbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65265rhbt.step/tps65265rhbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
00ac4ba9df2800c1, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).