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SN74ABT573APWR
Public Made by Adomby adom
Texas Instruments Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74ABT573APWR
Texas Instruments · Latches · TSSOP-20
SN74ABT573APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Buffered output-enable input that places the eight outputs in a normal logic state when low or in the high-impedance state when high, without affecting latch internal operation; tie to VCC through a pullup resistor to ensure high-Z during power up or down. |
| 2 | 1D | input | Data input for latch 1, passed to 1Q when LE is high and latched on the falling edge of LE. |
| 3 | 2D | input | Data input for latch 2, passed to 2Q when LE is high and latched on the falling edge of LE. |
| 4 | 3D | input | Data input for latch 3, passed to 3Q when LE is high and latched on the falling edge of LE. |
| 5 | 4D | input | Data input for latch 4, passed to 4Q when LE is high and latched on the falling edge of LE. |
| 6 | 5D | input | Data input for latch 5, passed to 5Q when LE is high and latched on the falling edge of LE. |
| 7 | 6D | input | Data input for latch 6, passed to 6Q when LE is high and latched on the falling edge of LE. |
| 8 | 7D | input | Data input for latch 7, passed to 7Q when LE is high and latched on the falling edge of LE. |
| 9 | 8D | input | Data input for latch 8, passed to 8Q when LE is high and latched on the falling edge of LE. |
| 10 | GND | power_in | Ground pin. |
| 11 | LE | input | Latch-enable input; latches are transparent when high and hold data when LE goes low. |
| 12 | 8Q | tri_state | 3-state output of latch 8 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 13 | 7Q | tri_state | 3-state output of latch 7 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 14 | 6Q | tri_state | 3-state output of latch 6 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 15 | 5Q | tri_state | 3-state output of latch 5 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 16 | 4Q | tri_state | 3-state output of latch 4 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 17 | 3Q | tri_state | 3-state output of latch 3 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 18 | 2Q | tri_state | 3-state output of latch 2 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 19 | 1Q | tri_state | 3-state output of latch 1 with high drive (-32 mA IOH, 64 mA IOL), high-impedance when OE is high. |
| 20 | VCC | power_in | Supply voltage pin, recommended 4.5 V to 5.5 V (absolute maximum -0.5 V to 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74ABT573APWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74abt573apwr-etched.step/sn74abt573apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74abt573apwr.step/sn74abt573apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (26 pp, sha256
498f2e95abd15739, retrieved 2026-10-10, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).