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CD4015BPWR
Public Made by Adomby adom
Texas Instruments Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4015BPWR
Texas Instruments · Shift Registers · TSSOP-16
CD4015BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLOCK B | input | Clock input of register B; shifts data on the positive-going clock transition, max clock frequency 3 MHz at 5 V, 6 MHz at 10 V, 8.5 MHz at 15 V. |
| 2 | Q4 B | output | Stage 4 parallel output of register B. |
| 3 | Q3 A | output | Stage 3 parallel output of register A. |
| 4 | Q2 A | output | Stage 2 parallel output of register A. |
| 5 | Q1 A | output | Stage 1 parallel output of register A. |
| 6 | RESET A | input | Reset input of register A; a high level resets all stages, minimum reset pulse width 200 ns at 5 V. |
| 7 | DATA A | input | Serial data input of register A; its level is transferred into the first stage on the positive-going clock transition. |
| 8 | VSS | power_in | Ground (VSS) supply reference terminal. |
| 9 | CLOCK A | input | Clock input of register A; shifts data on the positive-going clock transition, max clock frequency 3 MHz at 5 V, 6 MHz at 10 V, 8.5 MHz at 15 V. |
| 10 | Q4 A | output | Stage 4 parallel output of register A. |
| 11 | Q3 B | output | Stage 3 parallel output of register B. |
| 12 | Q2 B | output | Stage 2 parallel output of register B. |
| 13 | Q1 B | output | Stage 1 parallel output of register B. |
| 14 | RESET B | input | Reset input of register B; a high level resets all stages, minimum reset pulse width 200 ns at 5 V. |
| 15 | DATA B | input | Serial data input of register B; its level is transferred into the first stage on the positive-going clock transition. |
| 16 | VDD | power_in | Positive supply voltage, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4015BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4015bpwr-etched.step/cd4015bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4015bpwr.step/cd4015bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
1737b3cedb44d5c1, retrieved 2026-10-01, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).