component
TPS563201DDCR
Public Made by Adomby adom
Texas Instruments DC-DC Converters, SOT-23-THIN-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownTPS563201DDCR
Texas Instruments · DC-DC Converters · SOT-23-THIN-6
TPS563201DDCR from Texas Instruments, in a SOT-23-THIN-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground pin. Source terminal of the low-side power NFET and ground return for the controller circuit. Sensitive VFB return should tie to this GND at a single point. |
| 2 | SW | output | Switch node connection between the high-side NFET and the low-side NFET. Connects to the output inductor. Absolute max −2 V to 19 V. |
| 3 | VIN | power_in | Input voltage supply pin (4.5 V to 17 V). Drain terminal of the integrated high-side power NFET; requires local input decoupling capacitance. |
| 4 | VFB | input | Converter feedback input. Connect to the output through an external resistor divider that sets the output voltage; internal reference is ~0.768 V (0.749-0.787 V). |
| 5 | EN | input | Enable input control. Active high; pull above 1.6 V to enable, below 0.8 V to disable. Internal ~400 kΩ pull-down to GND; do not leave floating. |
| 6 | VBST | power_out | Bootstrap supply for the high-side NFET gate driver. Connect a 0.1 µF ceramic capacitor between VBST and SW. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOT-23-THIN-6 |
| Category | PMIC |
| Pins | 6 |
Ordering variants
Same part, different packaging or reel option.
TPS563201DDCRTPS563201DDCRDDCT
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply input voltage range | VIN | 4.5 | 17 | V | 4 | ||
| Input voltage range, VBST | VI | -0.1 | 23 | V | 4 | ||
| Input voltage range, VBST (10 ns transient) | VI | -0.1 | 26 | V | 10 ns transient | 4 | |
| Input voltage range, VBST (vs SW) | VI | -0.1 | 6 | V | vs SW | 4 | |
| Input voltage range, EN | VI | -0.1 | 17 | V | EN | 4 | |
| Input voltage range, VFB | VI | -0.1 | 5.5 | V | VFB | 4 | |
| Input voltage range, SW | VI | -1.8 | 17 | V | SW | 4 | |
| Input voltage range, SW (10 ns transient) | VI | -3.5 | 20 | V | SW, 10 ns transient | 4 | |
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| VIN, EN input voltage | -0.3 | 19 | V | Over operating free-air temperature range | 3 | ||
| VBST input voltage | -0.3 | 25 | V | Over operating free-air temperature range | 3 | ||
| VBST input voltage (10 ns transient) | -0.3 | 27 | V | 10 ns transient | 3 | ||
| VBST input voltage (vs SW) | -0.3 | 6.5 | V | vs SW | 3 | ||
| VFB input voltage | -0.3 | 6.5 | V | Over operating free-air temperature range | 3 | ||
| SW input voltage | -2 | 19 | V | Over operating free-air temperature range | 3 | ||
| SW input voltage (10 ns transient) | -3.5 | 21 | V | 10 ns transient | 3 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 3 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 3 | ||
| Junction-to-ambient thermal resistance (DDC, 6 pins) | RθJA | 92.6 | °C/W | 4 | |||
| Junction-to-case (top) thermal resistance (DDC, 6 pins) | RθJC(top) | 48.5 | °C/W | 4 | |||
| Junction-to-board thermal resistance (DDC, 6 pins) | RθJB | 15.5 | °C/W | 4 | |||
| Junction-to-top characterization parameter (DDC, 6 pins) | ψJT | 2.5 | °C/W | 4 | |||
| Junction-to-board characterization parameter (DDC, 6 pins) | ψJB | 15.5 | °C/W | 4 | |||
| Operating non-switching supply current (TPS563201) | IVIN | 380 | 520 | µA | VIN current, EN = 5 V, VFB = 0.8 V | 5 | |
| Shutdown supply current | IVINSDN | 1 | 10 | µA | VIN current, EN = 0 V | 5 | |
| EN high-level input voltage | VENH | 1.6 | V | EN | 5 | ||
| EN low-level input voltage | VENL | 0.8 | V | EN | 5 | ||
| EN pin resistance to GND | REN | 225 | 400 | 900 | kΩ | VEN = 12 V | 5 |
| VFB threshold voltage (Eco-mode operation) | VFBTH | 774 | mV | VO = 1.05 V, IO = 10 mA, Eco-mode operation | 5 | ||
| VFB threshold voltage (continuous mode operation) | VFBTH | 749 | 768 | 787 | mV | VO = 1.05 V, continuous mode operation | 5 |
| VFB input current | IVFB | -0.1 | 0 | 0.1 | µA | VFB = 0.8 V | 5 |
| High-side switch resistance | RDS(on)h | 95 | mΩ | TA = 25°C, VBST – SW = 5.5 V | 5 | ||
| Low-side switch resistance | RDS(on)l | 57 | mΩ | TA = 25°C | 5 | ||
| Current limit | Iocl | 3.3 | 4.2 | 5.1 | A | DC current, VOUT = 1.05 V, L1 = 1.5 µH | 5 |
| Thermal shutdown threshold | TSDN | 172 | °C | Shutdown temperature | 5 | ||
| Thermal shutdown hysteresis | TSDN | 37 | °C | Hysteresis | 5 | ||
| Minimum off time | tOFF(MIN) | 220 | 310 | ns | VFB = 0.5 V | 5 | |
| Soft-start time | Tss | 1 | ms | Internal soft-start time | 5 | ||
| Switching frequency | Fsw | 580 | kHz | VIN = 12 V, VO = 1.05 V, FCCM mode | 5 | ||
| Output UVP threshold | VUVP | 65 | % | Hiccup detect (H > L) | 5 | ||
| Hiccup on time | THICCUP_WAIT | 1.8 | ms | 5 | |||
| Hiccup time before restart | THICCUP_RE | 15 | ms | 5 | |||
| UVLO wake-up VIN voltage | UVLO | 4 | 4.3 | V | Wake up VIN voltage | 5 | |
| UVLO shutdown VIN voltage | UVLO | 3.3 | 3.6 | V | Shutdown VIN voltage | 5 | |
| UVLO hysteresis VIN voltage | UVLO | 0.4 | V | Hysteresis VIN voltage | 5 |
CAD (KiCad official)
- Symbol:
TPS563201DDCR - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23-THIN-6 (KiCad packages3D, STEP)
- 3D model files:
tps563201ddcr-etched.step/tps563201ddcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps563201ddcr.step/tps563201ddcr.glbare the bare package body.
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
tps563201ddcr.step |
97 KB | You want the bare part, or you mark your own boards. |
tps563201ddcr-etched.step |
2.7 MB | You want the part with TPS563201DDCR already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 638 faces against 117 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (24 pp, sha256
bcaa25f9478f48ef, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).