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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DS90UB935TRHBTQ1

Texas Instruments · Serializers, Deserializers · VQFN-32(5x5)

DS90UB935TRHBTQ1 from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CSI_D1P	input	CSI-2 data lane 1 positive D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
2	CSI_D1N	input	CSI-2 data lane 1 negative D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
3	CSI_D0P	input	CSI-2 data lane 0 positive D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
4	CSI_D0N	input	CSI-2 data lane 0 negative D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
5	CSI_CLKP	input	CSI-2 clock positive D-PHY input, connect to a CSI-2 clock source with matched 100Ω (±5%) interconnect.
6	CSI_CLKN	input	CSI-2 clock negative D-PHY input, connect to a CSI-2 clock source with matched 100Ω (±5%) interconnect.
7	RES0	input	Reserved pin, connect to GND.
8	PDB	input	Power-down bar input with internal 1MΩ pull-down; high (1.8V) enables the device, low powers it down, and it is not 3.3V tolerant.
9	LPF1	passive	Loop filter 1, connect a 0.022µF capacitor to VDDPLL (pin 11) as described in section 7.2.2.4.
10	VDDPLL_CAP	passive	Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail.
11	VDDPLL	power_in	1.8V (±5%) analog PLL supply pin, typically decoupled with 1µF and 0.01µF to ground.
12	LPF2	passive	Loop filter 2, connect a 0.1µF capacitor to GND as described in section 7.2.2.4.
13	DOUT-	bidirectional	FPD-Link III negative input/output pin, must be AC-coupled.
14	DOUT+	bidirectional	FPD-Link III positive input/output pin, must be AC-coupled.
15	VDDDRV_CAP	passive	Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail.
16	VDDDRV	power_in	1.8V (±5%) analog supply pin, typically decoupled with 1µF and 0.01µF to ground.
17	GPIO_0	bidirectional	General-purpose I/O that can also sense voltage; defaults to input with 300kΩ (typ) internal pull-down at power-up.
18	GPIO_1	bidirectional	General-purpose I/O that can also sense voltage; defaults to input with 300kΩ (typ) internal pull-down at power-up.
19	CLK_OUT/IDX	bidirectional	Strap input at PDB low-to-high sets I2C pull-up voltage and device address via resistor divider, then becomes CLK_OUT; minimum 35kΩ load when CLK_OUT is used.
20	CLKIN	input	Reference clock input for non-synchronous external clock mode; may be left open if unused.
21	MODE	input	Mode select strap input, sampled at PDB low-to-high via a resistor divider from VDD18 to GND.
22	RES1	input	Reserved pin, do not connect (leave floating).
23	I2C_SDA	bidirectional	Open-drain I2C data pin, pulled up to 1.8V or 3.3V depending on IDX setting.
24	I2C_SCL	bidirectional	Open-drain I2C clock pin, pulled up to 1.8V or 3.3V depending on IDX setting.
25	VDDD	power_in	1.8V (±5%) supply pin, typically decoupled with 1µF and 0.01µF to ground.
26	VDDD_CAP	passive	Internal regulator decoupling connection, typically 10µF, 0.1µF and 0.01µF to ground; do not connect to an external supply rail.
27	GPIO_2	bidirectional	General-purpose I/O defaulting to input with 300kΩ (typ) internal pull-down at power-up.
28	GPIO_3	bidirectional	General-purpose I/O defaulting to input with 300kΩ (typ) internal pull-down at power-up.
29	CSI_D3P	input	CSI-2 data lane 3 positive D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
30	CSI_D3N	input	CSI-2 data lane 3 negative D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
31	CSI_D2P	input	CSI-2 data lane 2 positive D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
32	CSI_D2N	input	CSI-2 data lane 2 negative D-PHY input, connect to a CSI-2 source with matched 100Ω (±5%) interconnect; may be left floating if unused.
33	GND	power_in	Exposed die attach pad (DAP) at the package center, connect to the ground plane.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-32(5x5)
Category	Interface
Pins	33

CAD (KiCad official)

Symbol: DS90UB935TRHBTQ1
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
3D model files: ds90ub935trhbtq1-etched.step / ds90ub935trhbtq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ds90ub935trhbtq1.step / ds90ub935trhbtq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (88 pp, sha256 e402e3a7c9adfc08, retrieved 2026-10-12, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF