component
ISL6545CBZ-T
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RENESAS DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownISL6545CBZ-T
RENESAS · DC-DC Converters · SOIC-8
ISL6545CBZ-T from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | power_out | Provides the ground-referenced bias for the upper MOSFET driver, a bootstrap voltage equal to VCC minus the on-chip boot diode drop, referenced to PHASE. |
| 2 | UGATE | output | Connect to the gate of the upper MOSFET to provide the PWM-controlled gate drive, and monitor it for adaptive shoot-through protection to detect when the upper MOSFET has turned off. |
| 3 | GND | power_in | Signal and power ground for the IC; tie to the ground island or plane through the lowest impedance connection available. |
| 4 | LGATE/OCSET | output | Connect to the gate of the lower MOSFET to provide PWM-controlled gate drive from VCC, and during a short period after POR or shutdown release, a resistor from this pin to GND (ROCSET) sets the overcurrent trip point using the nominal 21.5 µA OCSET current source. |
| 5 | VCC | power_in | Bias supply for the controller and the lower MOSFET gate drive; an internal 5V regulator supplies bias when VCC rises above 6.5V, and a well-decoupled 5V or 12V supply should be connected here. |
| 6 | FB | input | Inverting input of the internal error amplifier, where a resistor divider from the output to GND sets the regulation voltage against the 0.6V internal reference. |
| 7 | COMP/SD | bidirectional | Multiplexed pin that serves as the error amplifier output during soft-start and normal operation and as the shutdown input, where pulling it below the 0.4V nominal disable threshold disables the controller and an external pull-down must overcome up to 5mA of output current. |
| 8 | PHASE | passive | Connect to the upper MOSFET source and lower MOSFET drain; it is the sink for the UGATE driver, monitors the lower MOSFET voltage drop for overcurrent protection, and is monitored by shoot-through protection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage VCC (recommended operating) | VCC | 6.5 | 14.4 | V | 4 | ||
| Ambient Temperature Range, ISL6545C | 0 | 70 | °C | 4 | |||
| Junction Temperature Range | -40 | 125 | °C | 4 | |||
| Supply Voltage VCC (absolute maximum, GND - 0.3V to 15V) | VCC | -0.3 | 15 | V | 4 | ||
| BOOT Voltage (GND - 0.3V to 36V) | VBOOT | -0.3 | 36 | V | 4 | ||
| PHASE Voltage (GND - 8V for <400ns, 20µJ, to 30V for <200ns, VBOOT-GND<36V) | VPHASE | -8 | 30 | V | 4 | ||
| LGATE/OCSET Voltage (GND - 5V for <100ns, 2µJ) | VLGATE/OCSET | -5 | V | 4 | |||
| Upper Driver Supply Voltage VBOOT - VPHASE | VBOOT-VPHASE | 15 | V | 4 | |||
| FB, COMP/SD Voltage (GND - 0.3V to 6V) | VFB, VCOMP/SD | -0.3 | 6 | V | 4 | ||
| ESD Human Body Model | 1.5 | kV | 4 | ||||
| ESD Machine Model | 150 | V | 4 | ||||
| ESD Charged Device Model | 1 | kV | 4 | ||||
| Maximum Junction Temperature (Plastic Package) | TJ | 150 | °C | 4 | |||
| Maximum Storage Temperature Range | -65 | 150 | °C | 4 | |||
| Thermal Resistance, junction to ambient, SOIC package | θJA | 95 | °C/W | 4 | |||
| Rising VCC POR Threshold | VPOR | 3.9 | 4.1 | 4.3 | V | 4 | |
| VCC POR Threshold Hysteresis | 0.3 | 0.35 | 0.4 | V | 4 | ||
| Switching Frequency, ISL6545C | fOSC | 270 | 300 | 330 | kHz | ISL6545C | 4 |
| Reference Voltage Tolerance, ISL6545C | -1 | 1 | % | ISL6545C | 4 | ||
| Input Bias Supply Current | IVCC | 4 | 5.2 | mA | VCC = 12V; disabled | 4 | |
| Disable Threshold (COMP/SD pin) | VDISABLE | 0.375 | 0.4 | 0.425 | V | 5 | |
| OCSET Current Source, ISL6545C | IOCSET | 19.5 | 21.5 | 23.5 | µA | ISL6545C; LGATE/OCSET = 0V | 5 |
| Ramp Amplitude | ΔVOSC | 1.5 | VP-P | 4 | |||
| Nominal Reference Voltage | VREF | 0.6 | V | 4 | |||
| DC Gain | GAIN | 96 | dB | 4 | |||
| Gain-Bandwidth Product | GBWP | 20 | MHz | 4 | |||
| Slew Rate | SR | 9 | V/µs | 4 | |||
| Upper Gate Source Impedance (VCC=14.5V) | RUG-SRCh | 3 | Ω | VCC = 14.5V; I = 50mA | 4 | ||
| Upper Gate Sink Impedance (VCC=14.5V) | RUG-SNKh | 2.7 | Ω | VCC = 14.5V; I = 50mA | 4 | ||
| Lower Gate Source Impedance (VCC=14.5V) | RLG-SRCh | 2.4 | Ω | VCC = 14.5V; I = 50mA | 4 | ||
| Lower Gate Sink Impedance (VCC=14.5V) | RLG-SNKh | 2 | Ω | VCC = 14.5V; I = 50mA | 4 | ||
| Upper Gate Source Impedance (VCC=4.25V) | RUG-SRCl | 3.5 | Ω | VCC = 4.25V; I = 50mA | 5 | ||
| Upper Gate Sink Impedance (VCC=4.25V) | RUG-SNKl | 2.7 | Ω | VCC = 4.25V; I = 50mA | 5 | ||
| Lower Gate Source Impedance (VCC=4.25V) | RLG-SRCl | 2.75 | Ω | VCC = 4.25V; I = 50mA | 5 | ||
| Lower Gate Sink Impedance (VCC=4.25V) | RLG-SNKl | 2.1 | Ω | VCC = 4.25V; I = 50mA | 5 |
CAD (KiCad official)
- Symbol:
ISL6545CBZ-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
isl6545cbz-t-etched.step/isl6545cbz-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);isl6545cbz-t.step/isl6545cbz-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: RENESAS datasheet (16 pp, sha256
a8ebad34834a518d, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).