COS6212Q24R from COSINE, in a QFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	D1_IN+	input	Amplifier D1 noninverting input.
2	D2_IN+	input	Amplifier D2 noninverting input.
3	DGND	power_in	Ground reference for bias control pins; the DGND pin voltage ranges from VS- to (VS+ - 5 V).
4	IADJ	input	Bias current adjustment pin, default connected through 25kΩ to VS-.
5	VCM	output	Common-mode buffer output with a common-mode offset voltage of ±5 mV.
6	FLAG	output	Active-low error flag output that indicates an output fault condition (optional); it is an open-collector output that pulls low under fault conditions.
7	NC	unconnected	No connection; no internal connection.
8	NC	unconnected	No connection; no internal connection.
9	NC	unconnected	No connection; no internal connection.
10	NC	unconnected	No connection; no internal connection.
11	NC	unconnected	No connection; no internal connection.
12	NC	unconnected	No connection; no internal connection.
13	NC	unconnected	No connection; no internal connection.
14	NC	unconnected	No connection; no internal connection.
15	NC	unconnected	No connection; no internal connection.
16	NC	unconnected	No connection; no internal connection.
17	D2_OUT	output	Amplifier D2 output.
18	D2_IN-	input	Amplifier D2 inverting input.
19	D1_IN-	input	Amplifier D1 inverting input.
20	D1_OUT	output	Amplifier D1 output.
21	VS+	power_in	Positive power-supply connection; the supply voltage range is 8 V to 40 V.
22	VS-	power_in	Negative power-supply connection.
23	BIAS-1	input	Bias mode control, LSB; the device defaults to shutdown if no signal is present on the bias pins.
24	BIAS-2	input	Bias mode control, MSB; the device defaults to shutdown if no signal is present on the bias pins.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	COSINE
Package	QFN-24-EP(4x5)
Category	Operational Amplifier/Comparator
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power Supply voltage (absolute maximum)	VS+ to VS-			44	V		4
Storage Temperature Range	TS	-65		150	°C		4
Junction Temperature	TJ			150	°C		4
Operating Temperature Range (absolute maximum table)	TO	-40		85	°C		4
ESD Susceptibility HBM				5000	V		4
Supply Voltage (recommended)	Vs	8		40	V		4
Operating ambient temperature (recommended)	TA	-40		85	°C		4
Operating voltage range	Vs	8	12	40	V		5
Bias control pin voltage range		0	3.3	24	V	With respect to DGNG	5
Common-mode offset voltage	VCM-OS	-5		5	mV		5
Input Offset Voltage	VOS	-50	2	50	mV	-40 to 85°C	6
Noninverting Input Bias Current	IBP	-1		1	μA		6
Inverting Input Bias Current	IBN	-2		2	μA		6
Common-Mode input Range	VCM	-3		3	V		6
Output Voltage Swing	Vo	-8.8		8.8	V	RL=100Ω, Rs=0Ω	6
Output Voltage Swing	Vo	-8.1		8.1	V	RL=50Ω, Rs=0Ω	6
Output Voltage Swing	Vo	-7.1		7.1	V	RL=25Ω, Rs=0Ω	6
Output Current (Sourcing and Sinking)		-284		284	mA	RL=25Ω, Rs=0Ω	6
Power supply quiescent current, Full bias	IQ		23		mA	Full bias (BIAS1=0, BIAS2=0)	5
Power supply quiescent current, Mid bias	IQ		18		mA	Mid bias (BIAS1=1, BIAS2=0)	5
Power supply quiescent current, Low bias	IQ		16		mA	Low bias (BIAS1=0, BIAS2=1)	5
Power supply quiescent current, Shutdown	IQ		0.2		mA	Shutdown (BIAS1=1, BIAS2=1)	5
Current through DGND pin			0.2		μA	Full bias (BIAS1=0, BIAS2=0)	5
Positive power supply rejection ratio	+PSRR		90		dB	Differential	5
Negative power supply rejection ratio	-PSRR		90		dB	Differential	5
Bias control pin logic threshold, Logic 1			1.9		V	Logic 1, with respect to DGND	5
Bias control pin logic threshold, Logic 0			0.8		V	Logic 0, with respect to DGND	5
Bias control pin current, logic 0			10		μA	BIAS1, BIAS2=0.5V (logic 0)	5
Bias control pin current, logic 1			0.26		μA	BIAS1, BIAS2=3.3V (logic 1)	5
Common-mode output resistance, DC-coupled inputs			520		Ω	DC-coupled inputs	5
Common-mode output resistance, AC-coupled inputs			70		Ω	AC-coupled inputs	5
Open-loop transimpedance gain	ZOL		100		kΩ		6
Common-Mode Rejection Ratio	CMRR		70		dB		6
Inverting input resistance			150		Ω		6
Short-circuit output current			0.8		A		6
Signal bandwidth	BW		20		MHz	G=5V/V, RF=1.5kΩ, Vo=2Vpp	6
Slew rate (20% to 80%)	SR		500		V/μs	Vo=16Vpp	6
Rise and fall time (10% to 90%)			16		ns	Vo=2Vpp	6
1MHz harmonic distortion, 2nd-order			-122		dBc	Vo=4Vpp, RL=50Ω, 2nd-order	6
1MHz harmonic distortion, 3rd-order			-65		dBc	Vo=4Vpp, RL=50Ω, 3rd-order	6
6MHz harmonic distortion, 2nd-order			-86		dBc	Vo=4Vpp, RL=50Ω, 2nd-order	6
6MHz harmonic distortion, 3rd-order			-56		dBc	Vo=4Vpp, RL=50Ω, 3rd-order	6
Junction to Ambient Thermal Resistance	θJA		43.4		°C/W		4
Junction to Case (Bottom) Thermal Resistance	θJCbot		9.3		°C/W		4

CAD (KiCad official)

Symbol: COS6212Q24R
Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
3D model: QFN-24-EP(4x5) (KiCad packages3D, STEP)
3D model files: cos6212q24r-etched.step / cos6212q24r-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cos6212q24r.step / cos6212q24r.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: COSINE datasheet (12 pp, sha256 14c1027226fff32c, retrieved 2026-11-04, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

COS6212Q24R

Verified COS6212Q24R

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README