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ms1224

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by Ray

Hangzhou Ruimeng Tech LVDS ICs, SSOP-28-208mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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MS1224

Hangzhou Ruimeng Tech · LVDS ICs · SSOP-28-208mil

MS1224 from Hangzhou Ruimeng Tech, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog ground for the internal PLL and analog blocks. Tie all AGND pins directly to the board ground plane.
2 RCLK_R/F input LVTTL input that selects the RCLK edge used to latch ROUT[0:9] data. Low = falling-edge filtering; High = rising-edge filtering.
3 REFCLK input LVTTL reference clock input for the receive PLL, 10 MHz to 80 MHz. Frequency tolerance ±100 ppm; duty cycle 30% - 70%; edge time ≤6 ns.
4 AVCC power_in Analog 3.3 V supply for the PLL and analog circuitry (3.0 V - 3.6 V, 3.3 V typical). Decouple locally to AGND.
5 RI+ input LVDS differential serial data input, positive side. Differential threshold ±50 mV; common-mode range VID/2 to (2.4 V - VID/2). Pair with RI- across a 100 Ω termination.
6 RI- input LVDS differential serial data input, negative side. Paired with RI+ (pin 5); requires 100 Ω differential termination close to the receiver.
7 PWRDN input Active-low LVTTL power-down input. Driving low (>=16 ns) disables the PLL, forces outputs to high-Z and places the device in a low-power sleep drawing microamps of ICC. Drive high for normal operation.
8 REN input Active-low LVTTL receiver-enable input. Low forces ROUT0-ROUT9 and RCLK into high-impedance while /LOCK remains active to track PLL state. High enables the parallel outputs.
9 RCLK output Recovered LVTTL parallel-data clock output used to latch ROUT0-ROUT9. Runs at the recovered word rate (10 MHz - 80 MHz); output edge selected by RCLK_R/F.
10 LOCK output Active-low LVTTL lock-status output. Goes low when the deserializer PLL is locked to the embedded clock; high indicates loss of lock and the parallel outputs (and RCLK) are invalid/high-Z.
11 AVCC power_in Analog 3.3 V supply for the PLL and analog circuitry (3.0 V - 3.6 V). Bypass close to the pin with AGND return.
12 AGND power_in Analog ground return for the PLL and analog circuitry.
13 AGND power_in Analog ground return for the PLL and analog circuitry.
14 DGND power_in Digital ground return for the LVTTL output drivers and digital core.
15 ROUT9 output Parallel LVTTL data output, bit 9 (MSB of the 10-bit recovered word). VOH >= 2.2 V at IOH = -5 mA; VOL <= 0.5 V at IOL = 5 mA. Valid when /LOCK is low.
16 ROUT8 output Parallel LVTTL data output, bit 8. Latched on the RCLK edge selected by RCLK_R/F.
17 ROUT7 output Parallel LVTTL data output, bit 7. Latched on the RCLK edge selected by RCLK_R/F.
18 ROUT6 output Parallel LVTTL data output, bit 6. Latched on the RCLK edge selected by RCLK_R/F.
19 ROUT5 output Parallel LVTTL data output, bit 5. Latched on the RCLK edge selected by RCLK_R/F.
20 DGND power_in Digital ground return for the LVTTL output drivers.
21 DVCC power_in Digital 3.3 V supply (3.0 V - 3.6 V) for the LVTTL output drivers and digital core. Decouple close to the pin.
22 DGND power_in Digital ground return for the LVTTL output drivers.
23 DVCC power_in Digital 3.3 V supply (3.0 V - 3.6 V) for the LVTTL output drivers and digital core.
24 ROUT4 output Parallel LVTTL data output, bit 4. Latched on the RCLK edge selected by RCLK_R/F.
25 ROUT3 output Parallel LVTTL data output, bit 3. Latched on the RCLK edge selected by RCLK_R/F.
26 ROUT2 output Parallel LVTTL data output, bit 2. Latched on the RCLK edge selected by RCLK_R/F.
27 ROUT1 output Parallel LVTTL data output, bit 1. Latched on the RCLK edge selected by RCLK_R/F.
28 ROUT0 output Parallel LVTTL data output, bit 0 (LSB of the 10-bit recovered word). Latched on the RCLK edge selected by RCLK_R/F.

Key specifications

Parameter Value
Manufacturer Hangzhou Ruimeng Tech
Package SSOP-28-208mil
Category Interface
Pins 28

CAD (KiCad official)

  • Symbol: MS1224
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Hangzhou Ruimeng Tech datasheet (None pp, sha256 a2a820963051c0eb, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

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