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CY95F698KPMC-G-UNE2

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Cypress Semicon CYPRESS, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY95F698KPMC-G-UNE2

Cypress Semicon · CYPRESS · LQFP-48(7x7)

CY95F698KPMC-G-UNE2 from Cypress Semicon, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PG2 bidirectional General-purpose I/O port (hysteresis CMOS); also subclock I/O oscillation pin X1A and MPG waveform sequencer position-detection trigger input SNI2.
2 PG1 bidirectional General-purpose I/O port (hysteresis CMOS); also subclock input oscillation pin X0A and MPG waveform sequencer position-detection trigger input SNI1.
3 VCC power_in Power supply pin; the recommended operating supply range is 2.88 V to 5.5 V.
4 C passive Decoupling capacitor connection pin; connect a ceramic capacitor CS of 0.022 µF to 1 µF with the shortest possible distance to VSS.
5 P40 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also 8/10-bit A/D converter analog input AN08.
6 P41 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also 8/10-bit A/D converter analog input AN09.
7 P42 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also 8/10-bit A/D converter analog input AN10.
8 P43 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also 8/10-bit A/D converter analog input AN11.
9 P44 bidirectional General-purpose I/O port (hysteresis CMOS); also 16-bit reload timer ch.1 output TO1.
10 P45 bidirectional General-purpose I/O port (hysteresis CMOS); also LIN-UART clock I/O SCK.
11 P46 bidirectional General-purpose I/O port (hysteresis CMOS); also LIN-UART data output SOT.
12 P47 bidirectional General-purpose I/O port (CMOS input level); also LIN-UART data input SIN.
13 P10 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit PPG ch.1 output PPG10, which is mapped to P64 when SYSC:PPGSEL=1.
14 P11 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit PPG ch.1 output PPG11, which is mapped to P65 when SYSC:PPGSEL=1.
15 P12 bidirectional General-purpose I/O port (hysteresis CMOS, no pull-up); also DBG debug communication pin, which requires an external pull-up of 2 kΩ or above.
16 P13 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit PPG ch.0 output PPG00, which is mapped to P62 when SYSC:PPGSEL=1.
17 P14 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit PPG ch.0 output PPG01, which is mapped to P63 when SYSC:PPGSEL=1.
18 P15 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit PPG ch.2 output PPG20, which is mapped to P66 when SYSC:PPGSEL=1.
19 P16 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit PPG ch.2 output PPG21, which is mapped to P67 when SYSC:PPGSEL=1.
20 P17 bidirectional General-purpose I/O port (hysteresis CMOS); also trigger input SNI0 for the position detection function of the MPG waveform sequencer.
21 P70 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit composite timer ch.0 output TO00.
22 P71 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit composite timer ch.0 output TO01.
23 P72 bidirectional General-purpose I/O port (CMOS, N-ch open drain); also I2C bus interface ch.0 clock I/O SCL, with open-drain application voltage up to VSS + 5.5 V.
24 P73 bidirectional General-purpose I/O port (CMOS, N-ch open drain); also I2C bus interface ch.0 data I/O SDA, with open-drain application voltage up to VSS + 5.5 V.
25 P74 bidirectional General-purpose I/O port (hysteresis CMOS); also 8/16-bit composite timer ch.0 clock input EC0.
26 P75 bidirectional General-purpose I/O port (hysteresis CMOS); also UART/SIO ch.0 clock I/O UCK0.
27 P76 bidirectional General-purpose I/O port (hysteresis CMOS); also UART/SIO ch.0 data output UO0.
28 P77 bidirectional General-purpose I/O port (hysteresis CMOS); also UART/SIO ch.0 data input UI0.
29 P60 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG waveform sequencer input DTTI.
30 P61 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also 16-bit reload timer ch.1 input TI1.
31 P62 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG output OPT0, 8/16-bit PPG ch.0 output PPG00 and composite timer ch.1 output TO10.
32 P63 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG output OPT1, 8/16-bit PPG ch.0 output PPG01 and composite timer ch.1 output TO11.
33 P64 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG output OPT2, 8/16-bit PPG ch.1 output PPG10 and composite timer ch.1 clock input EC1.
34 P65 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG output OPT3 and 8/16-bit PPG ch.1 output PPG11.
35 P66 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG output OPT4, 8/16-bit PPG ch.2 output PPG20 and 16-bit PPG timer ch.1 output PPG1.
36 P67 bidirectional High-current general-purpose I/O port (8 mA/12 mA, hysteresis CMOS); also MPG output OPT5, 8/16-bit PPG ch.2 output PPG21 and 16-bit PPG timer ch.1 trigger input TRG1.
37 P00 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT00, A/D analog input AN00 and comparator ch.0 non-inverting input CMP0_P.
38 P01 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT01, A/D analog input AN01 and comparator ch.0 inverting input CMP0_N.
39 P02 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT02, A/D analog input AN02 and comparator ch.0 digital output CMP0_O.
40 P03 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT03, A/D analog input AN03 and comparator ch.1 non-inverting input CMP1_P.
41 P04 bidirectional General-purpose I/O port (CMOS/analog CMOS); also external interrupt INT04, A/D analog input AN04 and comparator ch.1 inverting input CMP1_N.
42 P05 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT05, A/D analog input AN05 and comparator ch.1 digital output CMP1_O.
43 P06 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT06 and A/D analog input AN06.
44 P07 bidirectional General-purpose I/O port (hysteresis/analog CMOS); also external interrupt INT07 and A/D analog input AN07.
45 PF2 bidirectional General-purpose I/O port (N-ch open drain output, hysteresis input); also reset pin RST, which requires an external pull-up of 2 kΩ or above.
46 PF0 input General-purpose I/O port (hysteresis input); also main clock input oscillation pin X0 for the main oscillation circuit.
47 PF1 bidirectional General-purpose I/O port (hysteresis input); also main clock I/O oscillation pin X1 for the main oscillation circuit.
48 VSS power_in Power supply pin (GND); connect to the power supply ground outside the device with low impedance.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VCC -0.3 6 V Referenced to VSS (VSS = 0.0 V) 85
Input voltage VI -0.3 6 V Referenced to VSS 85
Output voltage VO -0.3 6 V Referenced to VSS 85
Maximum clamp current ICLAMP -2 2 mA Applicable to specific pins 85
Total maximum clamp current Σ/ICLAMP/ 20 mA Applicable to specific pins 85
L level maximum output current IOL 15 mA 85
L level average current IOLAV1 4 mA Other than P60 to P67 85
L level average current (P60 to P67) IOLAV2 12 mA P60 to P67 85
L level total maximum output current ΣIOL 100 mA 85
L level total average output current ΣIOLAV 37 mA Total number of pins 85
H level maximum output current IOH -15 mA 85
H level average current IOHAV1 -4 mA Other than P60 to P67 85
H level average current (P60 to P67) IOHAV2 -8 mA P60 to P67 85
H level total maximum output current ΣIOH -100 mA 85
H level total average output current ΣIOHAV -47 mA Total number of pins 85
Power consumption Pd 320 mW 85
Operating temperature TA -40 85 °C 85
Storage temperature Tstg -55 150 °C 85
Power supply voltage VCC 2.88 5.5 V VSS = 0.0 V 87
Decoupling capacitor CS 0.022 1 µF Ceramic capacitor or equivalent frequency characteristics 87
Operating temperature TA -40 85 °C Other than on-chip debug mode 87
Operating temperature (on-chip debug mode) TA 5 35 °C On-chip debug mode 87
H level input voltage (P47, P72, P73, P77) VIHI 0.7 VCC CMOS input level; printed as 0.7 VCC min and VCC + 0.3 V max 88
H level input voltage (other than P47, P72, P73, P77, PF2) VIHS 0.8 VCC Hysteresis input 88
H level input voltage (PF2) VIHM 0.8 VCC Hysteresis input 88
L level input voltage (P47, P72, P73, P77) VILI 0.3 VCC CMOS input level; printed min VSS − 0.3 V 88
L level input voltage (other than P47, P72, P73, P77, PF2) VILS 0.2 VCC Hysteresis input; printed min VSS − 0.3 V 88
L level input voltage (PF2) VILM 0.2 VCC Hysteresis input; printed min VSS − 0.3 V 88
Open-drain output application voltage VD -0.3 5.5 V P12, P72, P73, PF2; referenced to VSS (0.0 V) 88
H level output voltage VOH1 -0.5 V IOH = −4 mA; other than P12, P60 to P67, PF2; printed VCC − 0.5 V 88
H level output voltage (P60 to P67) VOH2 -0.5 V IOH = −8 mA; printed VCC − 0.5 V 88
L level output voltage VOL1 0.4 V IOL = 4 mA; other than P60 to P67 88
L level output voltage (P60 to P67) VOL2 0.4 V IOL = 12 mA; P60 to P67 88
Input leak current (Hi-Z output leak current) ILI -5 5 µA 0.0 V < VI < VCC; internal pull-up resistor disabled 88
Internal pull-up resistor RPULL 25 50 100 kΩ VI = 0 V; internal pull-up resistor enabled; other than P12, P72, P73, PF0, PF1, PF2 88
Input capacitance CIN 5 15 pF f = 1 MHz; other than VCC and VSS 88
Power supply current (external clock, except Flash programming/erasing) ICC 4.9 5.8 mA FCH = 32 MHz, FMP = 16 MHz, main clock mode (divided by 2) 89
Power supply current during Flash memory programming and erasing ICC 10.5 13.8 mA FCH = 32 MHz, FMP = 16 MHz, main clock mode (divided by 2); during Flash programming and erasing 89
Power supply current, main sleep mode ICCS 2 3 mA FCH = 32 MHz, FMP = 16 MHz, main sleep mode (divided by 2) 89
Power supply current, subclock mode ICCL 75.9 145 µA FCL = 32 kHz, FMPL = 16 kHz, subclock mode (divided by 2); TA = +25 °C 89
Power supply current, subsleep mode (deep standby) ICCLS 12.7 16 µA FCL = 32 kHz, FMPL = 16 kHz, subsleep mode (divided by 2); TA = +25 °C; in deep standby mode 89
Power supply current, watch mode (deep standby) ICCT 11 13 µA FCL = 32 kHz, watch mode, main stop; TA = +25 °C; in deep standby mode 89
Power supply current, main CR PLL clock mode ICCMPLL 5.2 6.8 mA FMCRPLL = 16 MHz, FMP = 16 MHz, multiplied by 4; TA = +25 °C 89
Power supply current, main CR clock mode ICCMCR 1.4 4.6 mA FCRH = 4 MHz, FMP = 4 MHz 89
Power supply current, time-base timer mode (deep standby) ICCTS 387 455 µA FCH = 32 MHz, time-base timer mode; TA = +25 °C; in deep standby mode 89
Main clock frequency (main oscillation) FCH 1 16.25 MHz When the main oscillation circuit is used (X0, X1) 91
Main clock frequency (external clock) FCH 1 32.5 MHz When the main external clock is used (X0, X1) 91
Main CR clock frequency FCRH 3.92 4 4.08 MHz Main CR clock used; 0 °C ≤ TA ≤ +70 °C 91
Main CR clock frequency (full temperature range) FCRH 3.8 4 4.2 MHz Main CR clock used; −40 °C ≤ TA < 0 °C, +70 °C < TA ≤ +85 °C 91
Main CR PLL clock frequency (PLL multiplication rate 2) FMCRPLL 7.6 8 8.4 MHz PLL multiplication rate 2; −40 °C ≤ TA < 0 °C, +70 °C < TA ≤ +85 °C 91
Main CR PLL clock frequency (PLL multiplication rate 4) FMCRPLL 15.2 16 16.8 MHz PLL multiplication rate 4; −40 °C ≤ TA < 0 °C, +70 °C < TA ≤ +85 °C 91
Sub-CR clock frequency FCRL 50 100 150 kHz When the sub-CR clock is used 91
Total error -3 3 LSB 110
Linearity error -2.5 2.5 LSB 110
Differential linearity error -1.9 1.9 LSB 110
Compare time 3 10 µs 2.7 V ≤ VCC ≤ 5.5 V 110
Sampling time 0.941 µs 2.7 V ≤ VCC ≤ 5.5 V, external impedance < 3.3 kΩ, external capacitance 10 pF 110
Analog input current IAIN -0.3 0.3 µA 110
Comparator offset voltage -15 15 mV CMP0_P, CMP0_N, CMP1_P, CMP1_N 109
BGR output voltage VBGR 1.1495 1.21 1.2705 V 109

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin • Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, 26

CAD (KiCad official)

  • Symbol: CY95F698KPMC-G-UNE2
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cy95f698kpmc-g-une2-etched.step / cy95f698kpmc-g-une2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy95f698kpmc-g-une2.step / cy95f698kpmc-g-une2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (130 pp, sha256 c262b872ad46f6e0, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF