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FCM32F103C8T6

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Flashchip Microelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Contents

README

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FCM32F103C8T6

Flashchip Microelectronics · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

FCM32F103C8T6 from Flashchip Microelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected Marked NC (not connected) in the LQFP48/UFQFPN48 column of the pin definitions table.
2 PC13-TAMPER-RTC bidirectional General-purpose I/O PC13 with TAMPER-RTC function; the table gives no FT (5 V tolerant) marking for this pin.
3 PC14-OSC32_IN bidirectional General-purpose I/O PC14 multiplexed with OSC32_IN, the 32.768 kHz low-speed oscillator input used for the RTC.
4 PC15-OSC32_OUT bidirectional General-purpose I/O PC15 multiplexed with OSC32_OUT, the 32.768 kHz low-speed oscillator output used for the RTC.
5 OSC_IN input Input of the 4-16 MHz external crystal oscillator (HSE); listed as PD0 in the remap column.
6 OSC_OUT output Output of the 4-16 MHz external crystal oscillator (HSE); listed as PD1 in the remap column.
7 NRST bidirectional Reset pin with VIL(NRST) max 0.3VDD, VIH(NRST) min 0.445VDD+0.4 V, Schmitt hysteresis 200 mV typ and weak pull-up of 40 kΩ typ.
8 VSSA power_in Analog ground pin for the ADC, reset circuitry, RC oscillators and PLL, referenced to VSS.
9 VDDA power_in Analog supply 1.8-5.5 V for the ADC, reset circuitry, RC oscillators and PLL; VDDA must always be ≥ VDD and be powered first.
10 PA0-WKUP bidirectional General-purpose I/O PA0 with alternate functions WKUP, USART2_CTS, ADC12_IN0 and TIM2_CH1_ETR.
11 PA1 bidirectional General-purpose I/O PA1 with alternate functions USART2_RTS, ADC12_IN1 and TIM2_CH2.
12 PA2 bidirectional General-purpose I/O PA2 with alternate functions USART2_TX, ADC12_IN2 and TIM2_CH3.
13 PA3 bidirectional General-purpose I/O PA3 with alternate functions USART2_RX, ADC12_IN3 and TIM2_CH4.
14 PA4 bidirectional General-purpose I/O PA4 with alternate functions SPI1_NSS, USART2_CK and ADC12_IN4.
15 PA5 bidirectional General-purpose I/O PA5 with alternate functions SPI1_SCK and ADC12_IN5.
16 PA6 bidirectional General-purpose I/O PA6 with alternate functions SPI1_MISO, ADC12_IN6 and TIM3_CH1; TIM1_BKIN under remap.
17 PA7 bidirectional General-purpose I/O PA7 with alternate functions SPI1_MOSI, ADC12_IN7 and TIM3_CH2; TIM1_CH1N under remap.
18 PB0 bidirectional General-purpose I/O PB0 with alternate functions ADC12_IN8 and TIM3_CH3; TIM1_CH2N under remap.
19 PB1 bidirectional General-purpose I/O PB1 with alternate functions ADC12_IN9 and TIM3_CH4; TIM1_CH3N under remap.
20 PB2/BOOT1 bidirectional 5 V tolerant (FT) general-purpose I/O PB2 that also serves as the BOOT1 boot-select input.
21 PB10 bidirectional 5 V tolerant (FT) I/O PB10 with alternate functions I2C2_SCL, TIM2_CH3 and USART3_TX.
22 PB11 bidirectional 5 V tolerant (FT) I/O PB11 with alternate functions I2C2_SDA, USART3_RX and TIM2_CH4.
23 VSS_1 power_in Digital ground pin, referenced to VSS.
24 VDD_1 power_in Digital and I/O supply pin, VDD 1.8-5.5 V.
25 PB12 bidirectional 5 V tolerant (FT) I/O PB12 with alternate functions SPI2_NSS, I2C2_SMBAL, USART3_CK and TIM1_BKIN.
26 PB13 bidirectional 5 V tolerant (FT) I/O PB13 with alternate functions SPI2_SCK, USART3_CTS and TIM1_CH1N.
27 PB14 bidirectional 5 V tolerant (FT) I/O PB14 with alternate functions SPI2_MISO, USART3_RTS and TIM1_CH2N.
28 PB15 bidirectional 5 V tolerant (FT) I/O PB15 with alternate functions SPI2_MOSI and TIM1_CH3N.
29 PA8 bidirectional 5 V tolerant (FT) I/O PA8 with alternate functions USART1_CK, TIM1_CH1 and MCO.
30 PA9 bidirectional 5 V tolerant (FT) I/O PA9 with alternate functions USART1_TX and TIM1_CH2.
31 PA10 bidirectional 5 V tolerant (FT) I/O PA10 with alternate functions USART1_RX and TIM1_CH3.
32 PA11 bidirectional 5 V tolerant (FT) I/O PA11 with alternate functions USART1_CTS, CANRX, USBDM and TIM1_CH4.
33 PA12 bidirectional 5 V tolerant (FT) I/O PA12 with alternate functions USART1_RTS, CANTX, USBDP and TIM1_ETR.
34 PA13 bidirectional 5 V tolerant (FT) SWJ debug pin JTMS/SWDIO.
35 VSS_2 power_in Digital ground pin, referenced to VSS.
36 VDD_2 power_in Digital and I/O supply pin, VDD 1.8-5.5 V.
37 PA14 bidirectional 5 V tolerant (FT) SWJ debug pin JTCK/SWCLK.
38 PA15 bidirectional 5 V tolerant (FT) pin with JTDI as main debug function; TIM2_CH1_ETR and SPI1_NSS under remap.
39 PB3 bidirectional 5 V tolerant (FT) pin with JTDO as debug function; TIM2_CH2, TRACESWO and SPI1_SCK as alternates.
40 PB4 bidirectional 5 V tolerant (FT) pin with JNTRST as debug function; TIM3_CH1 and SPI1_MISO under remap.
41 PB5 bidirectional I/O PB5 (no FT marking in the table) with alternate functions I2C1_SMBAL, TIM3_CH2 and SPI1_MOSI.
42 PB6 bidirectional 5 V tolerant (FT) I/O PB6 with alternate functions I2C1_SCL, TIM4_CH1 and USART1_TX.
43 PB7 bidirectional 5 V tolerant (FT) I/O PB7 with alternate functions I2C1_SDA, TIM4_CH2 and USART1_RX.
44 BOOT0 input Boot mode input; together with the boot select option bits it selects user Flash, System Memory or SRAM boot at startup.
45 PB8 bidirectional 5 V tolerant (FT) I/O PB8 with alternate functions TIM4_CH3, I2C1_SCL and CANRX.
46 PB9 bidirectional 5 V tolerant (FT) I/O PB9 with alternate functions TIM4_CH4, I2C1_SDA and CANTX.
47 VSS_3 power_in Digital ground pin, referenced to VSS.
48 VDD_3 power_in Digital and I/O supply pin, VDD 1.8-5.5 V.

Key specifications

Parameter Value
Manufacturer Flashchip Microelectronics
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute maximum external main supply voltage VDD-VSS -0.3 5.8 V 29
Absolute maximum external I/O supply voltage VDDIO2-VSS -0.3 5.8 V 29
Absolute maximum external analog supply voltage VDDA-VSS -0.3 5.8 V 29
Allowed voltage difference for VDD>VDDA VDD-VDDA 0.3 V 29
Absolute maximum external backup supply voltage VBAT-VSS -0.3 5.8 V 29
Absolute maximum input voltage on TTa pins VIN 5.8 V TTa pins 29
Digital and I/O supply voltage (features) VDD 1.8 5.5 V 1
Operating temperature range, temperature code 6 -40 85 ℃ Temperature range code 6 per ordering scheme 48
VDD fall time rate 20 us/V 31
VDDA fall time rate 20 us/V 31
Power on/down reset threshold VPOR/PDR 1.51 1.58 1.65 V Falling edge 31
Power on/down reset threshold VPOR/PDR 1.54 1.62 1.7 V Rising edge 31
Reset temporization tRSTTEMPO 1.5 2.5 4.5 ms 31
PVD threshold 0 VPVD0 1.59 1.67 1.75 V Falling edge 31
PVD threshold 0 VPVD0 1.75 1.83 1.91 V Rising edge 31
PVD threshold 1 VPVD1 1.75 1.83 1.91 V Falling edge 31
PVD threshold 1 VPVD1 1.9 1.98 2.06 V Rising edge 31
PVD threshold 2 VPVD2 1.9 1.98 2.06 V Falling edge 31
PVD threshold 2 VPVD2 2.06 2.14 2.22 V Rising edge 31
PVD threshold 3 VPVD3 2.06 2.14 2.22 V Falling edge 31
PVD threshold 3 VPVD3 2.21 2.29 2.37 V Rising edge 31
PVD threshold 4 VPVD4 2.21 2.29 2.37 V Falling edge 31
PVD threshold 4 VPVD4 2.35 2.43 2.51 V Rising edge 31
PVD threshold 5 VPVD5 2.35 2.43 2.51 V Falling edge 31
PVD threshold 5 VPVD5 2.49 2.57 2.65 V Rising edge 31
PVD threshold 6 VPVD6 2.49 2.57 2.65 V Falling edge 31
PVD threshold 6 VPVD6 2.64 2.72 2.8 V Rising edge 31
PVD threshold 7 VPVD7 2.64 2.72 2.8 V Falling edge 31
PVD threshold 7 VPVD7 2.8 2.88 2.96 V Rising edge 31
Internal reference voltage VREFINT 1.16 1.2 1.26 V -40C<TA<+105 31
Internal reference voltage spread over the temperature range △VREFINNT 10 mV VDDA=3V 32
Internal reference voltage temperature coefficient TCoeff 100 ppm/C 32
Wakeup from stop mode tWUSTOP 2.8 5 us Regulator in run mode 32
User external clock source frequency fHSE_EXT 8 24 MHz 33
OSC_IN high or low time tW(HSEH), tW(HSEL) 15 ns 33
OSC_IN rise or fall time tr(HSE), tf(HSE) 20 ns 33
User external clock source frequency (LSE) fLSE_EXT 32.768 1000 KHz 33
OSC32_IN high or low time tW(LSEH), tW(LSEL) 450 ns 33
OSC32_IN rise or fall time tr(LSE), tf(LSE) 50 ns 33
HSE oscillator frequency fOSC_IN 4 8 16 MHz 33
Duty cycle (HSI8) DuCy 45 55 % 34
Accuracy of the HSI oscillator (factory calibrated) ACCHSI48 -1.84 2 % TA=-40 to 105 @SS 34
Accuracy of the HSI oscillator (factory calibrated) ACCHSI48 -1.58 1.76 % TA=-40 to 105@TT 34
Accuracy of the HSI oscillator (factory calibrated) ACCHSI48 -1.24 1.72 % TA=-40 to 105@FF 34
HSI8 oscillator power consumption IDDA(HSI8) 643 801 uA 34
LSI oscillator frequency fLSI 31.9 40 55.5 KHz 34
PLL input clock fPLL_IN 1 8 24 MHz 34
PLL multiplier output clock tPLL_OUT 16 96 MHz 34
PLL lock time tLOCK 30 100 us 34
I/O current injection, injected current IINJ -5 5 mA 35
Analog supply voltage VDDA 1.8 3.3 5.5 V 38
ADC clock frequency fADC 16 MHz 38
Offset error EO -3 1.5 3 LSB fPCLK=48MHz, fADC=16MHz, RAIN<10kΩ, VDDA=3V to 3.6V, TA=25C 38
Gain error EG -5 2 5 LSB fPCLK=48MHz, fADC=16MHz, RAIN<10kΩ, VDDA=3V to 3.6V, TA=25C 38
Differential linearity error ED -1.5 0.6 1.5 LSB fPCLK=48MHz, fADC=16MHz, RAIN<10kΩ, VDDA=3V to 3.6V, TA=25C 38
Integral linearity error EL -3 1.5 3 LSB fPCLK=48MHz, fADC=16MHz, RAIN<10kΩ, VDDA=3V to 3.6V, TA=25C 38
VSENSE linearity with temperature TL -2 1 2 C 39
Average slope Avg_Slope 4.2 4.28 4.36 mV/C 39
Voltage at 30C V30 1.423 1.425 1.43 V 39
Output low level voltage for an I/O pin, CMOS port VOL 0.4 V CMOS port, /IIO/ = 8mA, VDDIOx>= 2.7V 36

CAD (KiCad official)

  • Symbol: FCM32F103C8T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: fcm32f103c8t6-etched.step / fcm32f103c8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fcm32f103c8t6.step / fcm32f103c8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Flashchip Microelectronics datasheet (50 pp, sha256 afeb69aa679aa7c7, retrieved 2026-10-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF