component
SI3019-F-FT
Public Made by Adomby adom
SILICON LABS Telecommunication Interface ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSI3019-F-FT
SILICON LABS · Telecommunication Interface ICs · TSSOP-16
SI3019-F-FT from SILICON LABS, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | QE | passive | Transistor emitter that connects to the emitter of Q3. |
| 2 | DCT | passive | DC termination that provides dc termination to the telephone network. |
| 3 | RX | input | Receive input that serves as the receive-side input from the telephone network. |
| 4 | IB | passive | Internal bias that provides a bias voltage to the device. |
| 5 | C1B | passive | Isolation capacitor 1B that connects to one side of isolation capacitor C1 and is used to communicate with the system-side device. |
| 6 | C2B | passive | Isolation capacitor 2B that connects to one side of isolation capacitor C2 and is used to communicate with the system-side device. |
| 7 | VREG | passive | Voltage regulator that connects to an external capacitor to provide bypassing for an internal power supply. |
| 8 | RNG1 | passive | Ring 1 that connects through a resistor to the TIP lead of the telephone line and provides the ring and caller ID signals to the DAA. |
| 9 | RNG2 | passive | Ring 2 that connects through a resistor to the RING lead of the telephone line and provides the ring and caller ID signals to the DAA. |
| 10 | VREG2 | passive | Voltage regulator 2 that connects to an external capacitor to provide bypassing for an internal power supply. |
| 11 | SC | passive | SC connection that enables the external transistor network and should be tied through a 0 resistor to IGND. |
| 12 | QE2 | passive | Transistor emitter 2 that connects to the emitter of Q4. |
| 13 | QB | passive | Transistor base that connects to the base of transistor Q4. |
| 14 | DCT3 | passive | DC termination 3 that provides dc termination to the telephone network. |
| 15 | IGND | power_in | Isolated ground that connects to ground on the line-side interface. |
| 16 | DCT2 | passive | DC termination 2 that provides dc termination to the telephone network. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | SILICON LABS |
| Package | TSSOP-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Temperature (F-Grade) | TA | 0 | 25 | 70 | °C | F-Grade | 5 |
| DC Termination Voltage | VTR | 6 | V | IL = 20 mA, ILIM = 0; DCV = 00, MINI = 11, DCR = 0 | 6 | ||
| DC Termination Voltage | VTR | 9 | V | IL = 120 mA, ILIM = 0; DCV = 00, MINI = 11, DCR = 0 | 6 | ||
| DC Termination Voltage | VTR | 7.5 | V | IL = 20 mA, ILIM = 0; DCV = 11, MINI = 00, DCR = 0 | 6 | ||
| DC Termination Voltage | VTR | 40 | V | IL = 60 mA, ILIM = 1; DCV = 11, MINI = 00, DCR = 0 | 6 | ||
| DC Termination Voltage | VTR | 40 | V | IL = 50 mA, ILIM = 1; DCV = 11, MINI = 00, DCR = 0 | 6 | ||
| On-Hook Leakage Current | ILK | 5 | µA | VTR = -48 V | 6 | ||
| Operating Loop Current | ILP | 10 | 120 | mA | MINI = 00, ILIM = 0 | 6 | |
| Operating Loop Current | ILP | 10 | 60 | mA | MINI = 00, ILIM = 1 | 6 | |
| DC Ring Current | 1.5 | 3 | µA | dc current flowing through ring detection circuitry | 6 | ||
| Ring Detect Voltage | VRD | 13.5 | 15 | 16.5 | Vrms | RT2 = 0, RT = 0 | 6 |
| Ring Detect Voltage | VRD | 19.35 | 21.5 | 23.65 | Vrms | RT2 = 0, RT = 1 | 6 |
| Ring Detect Voltage | VRD | 40.5 | 45 | 49.5 | Vrms | RT2 = 1, RT = 1 | 6 |
| Ring Frequency | FR | 13 | 68 | Hz | 6 | ||
| Ringer Equivalence Number | REN | 0.2 | 6 | ||||
| Sample Rate | Fs | 8 | 16 | kHz | 8 | ||
| PCLK Input Frequency | PCLK | 256 | 8192 | kHz | 8 | ||
| Gain Accuracy | -0.5 | 0 | 0.5 | dB | 2-W to DTX, TXG2, RXG2, TXG3, and RXG3 = 0000 | 9 | |
| Transhybrid Balance | 20 | dB | 300-3.4 kHz, ZACIM = ZLINE | 9 | |||
| Two-Wire Return Loss | 25 | dB | 300-3.4 kHz, all ac terminations | 9 | |||
| DC Supply Voltage | VD | -0.5 | 3.6 | V | 9 | ||
| Input Current, Digital Input Pins (Si3050) | IIN | -10 | 10 | mA | 9 | ||
| Digital Input Voltage | VIND | -0.3 | V | printed as (VD + 0.3) | 9 | ||
| Ambient Operating Temperature Range | TA | -40 | 100 | °C | 9 | ||
| Storage Temperature Range | TSTG | -65 | 150 | °C | 9 | ||
| Thermal Resistance, Junction-to-Ambient (Si3011/18/19) | JA | 89 | °C/W | TSSOP-16 package | 5 |
CAD (KiCad official)
- Symbol:
SI3019-F-FT - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
si3019-f-ft-etched.step/si3019-f-ft-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);si3019-f-ft.step/si3019-f-ft.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: SILICON LABS datasheet (128 pp, sha256
c48c98a604cb0cd7, retrieved 2026-10-30, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).