74HC595PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	Q1	output	Parallel data output bit 1 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH. Bus driver output: sourcing/sinking up to ~6 mA at VCC = 4.5 V.
2	Q2	output	Parallel data output bit 2 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
3	Q3	output	Parallel data output bit 3 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
4	Q4	output	Parallel data output bit 4 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
5	Q5	output	Parallel data output bit 5 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
6	Q6	output	Parallel data output bit 6 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
7	Q7	output	Parallel data output bit 7 (MSB) from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
8	GND	power_in	Ground reference (0 V). Connect to system ground.
9	Q7S	output	Serial data output from the last stage of the shift register. Used to cascade multiple 74HC595 devices by tying to the next stage's DS input. Non-3-state; drives up to ~4 mA at VCC = 4.5 V.
10	MR	input	Master reset input, active LOW. A LOW level asynchronously clears the shift register (does not affect the storage register/parallel outputs). Must be held HIGH during normal shift operation.
11	SHCP	input	Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Equivalent to the SPI SCK for the shift stage; typical max frequency ~100 MHz at VCC = 6 V.
12	STCP	input	Storage register clock input (latch). On the LOW-to-HIGH transition of STCP, the contents of the shift register are transferred to the storage register and appear on Q0..Q7. Commonly called the 'latch' or 'RCK' pin.
13	OE	input	Output enable input, active LOW. LOW enables the Q0..Q7 parallel outputs; HIGH forces Q0..Q7 to a high-impedance OFF-state. Does not affect the state of the shift or storage registers.
14	DS	input	Serial data input. Sampled into shift register stage 0 on the LOW-to-HIGH edge of SHCP. Equivalent to SPI MOSI for cascaded shift-register chains.
15	Q0	output	Parallel data output bit 0 (LSB) from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.
16	VCC	power_in	Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC595) / 4.5 V to 5.5 V (74HCT595). Absolute maximum 7 V. Decouple locally with a 100 nF ceramic capacitor to GND.

Key specifications

Parameter	Value
Manufacturer	Nexperia
Package	TSSOP-16
Category	Logic
Pins	16

Ordering variants

74HC595PW
74HC595PWD
74HC595PWBQ
74HC595PWBZ

CAD (KiCad official)

Symbol: 74HC595PW
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)

3D model downloads

Two STEP files. Same geometry, different body top:

File	Size	Use it when
`74hc595pw.step`	205 KB	You want the bare part, or you mark your own boards.
`74hc595pw-etched.step`	2.2 MB	You want the part with `74HC595PW` already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 551 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Nexperia datasheet (21 pp, sha256 fa24207e780cd8c4, retrieved 2026-08-17, tier: manufacturer)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF