component
LN7910DT1WG
Public Made by Adomby adom
LRC MOSFETs, DFN-8(5x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLN7910DT1WG
LRC · MOSFETs · DFN-8(5x6)
LN7910DT1WG from LRC, in a DFN-8(5x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET, shared with pins 2 and 3; VGS is limited to ±20 V. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, shared with pins 1 and 3; VGS is limited to ±20 V. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, shared with pins 1 and 2; VGS is limited to ±20 V. |
| 4 | G | input | Gate terminal; threshold voltage is 2 V min, 3 V typ and 4 V max at ID=250µA, and VGS is limited to ±20 V. |
| 5 | D | passive | Drain terminal, shared with pins 6, 7 and 8; VDS is limited to 150 V. |
| 6 | D | passive | Drain terminal, shared with pins 5, 7 and 8; VDS is limited to 150 V. |
| 7 | D | passive | Drain terminal, shared with pins 5, 6 and 8; VDS is limited to 150 V. |
| 8 | D | passive | Drain terminal, shared with pins 5, 6 and 7; VDS is limited to 150 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | DFN-8(5x6) |
| Category | Transistors/Thyristors |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-Source Voltage | VDS | 150 | V | 1 | |||
| Gate-to-Source Voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous Drain Current | ID | 60 | A | TC=25℃ | 1 | ||
| Continuous Drain Current | ID | 53 | A | TC=75℃ | 1 | ||
| Continuous Drain Current | ID | 12.4 | A | TA=25℃ | 1 | ||
| Continuous Drain Current | ID | 11 | A | TA=75℃ | 1 | ||
| Pulsed Drain Current | IDM | 48 | A | 1 | |||
| Power Dissipation | PD | 104 | W | TC=25℃ | 1 | ||
| Power Dissipation | PD | 2.5 | W | TA=25℃ | 1 | ||
| Avalanche Energy | EAS | 39.2 | mJ | L=0.1mH | 1 | ||
| Avalanche Current | IAS | 28 | A | L=0.1mH | 1 | ||
| Operating Junction and Storage Temperature Range | Tj/Tstg | -55 | 150 | ℃ | 1 | ||
| Junction-to-Ambient Thermal Resistance | RθJA | 50 | ℃/W | 1 | |||
| Junction-to-Case Thermal Resistance | RθJC | 1.2 | ℃/W | 1 | |||
| Drain to Source Breakdown Voltage | BVDSS | 150 | V | VGS=0V, ID=250µA | 2 | ||
| Drain-to-Source Leakage Current | IDSS | 1 | uA | VDS=120V, VGS=0V | 2 | ||
| Gate-Body Leakage Current | IGSS | -100 | 100 | nA | VDS=0V, VGS=±20V | 2 | |
| Gate Threshold Voltage | VGS(th) | 2 | 3 | 4 | V | VDS=VGS, ID=250µA | 2 |
| Drain-to-Source On-Resistance | RDS(ON) | 9.5 | 11.5 | mΩ | VGS=10 V, ID=15 A | 2 | |
| Diode Forward Voltage | VSD | 0.8 | 1.2 | V | VGS=0 V, IS=20 A | 2 | |
| Gate Resistance | Rg | 2.8 | Ω | 2 |
CAD (KiCad official)
- Symbol:
LN7910DT1WG - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN-8(5x6) (KiCad packages3D, STEP)
- 3D model files:
ln7910dt1wg-etched.step/ln7910dt1wg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ln7910dt1wg.step/ln7910dt1wg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LRC datasheet (6 pp, sha256
40a90daec89f74c4, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).