component
MC74LVX4053DTR2G
Public Made by Adomby adom
onsemi Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMC74LVX4053DTR2G
onsemi · Analog Switches, Multiplexers · TSSOP-16
MC74LVX4053DTR2G from onsemi, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | passive | Analog input/output Y1 of the Y switch, connected to common Y15 when selected by input B with Enable LOW; the analog signal must stay between VEE and VCC. |
| 2 | Y0 | passive | Analog input/output Y0 of the Y switch, connected to common Y15 when selected by input B with Enable LOW; the analog signal must stay between VEE and VCC. |
| 3 | Z1 | passive | Analog input/output Z1 of the Z switch, connected to common Z4 when selected by input C with Enable LOW; the analog signal must stay between VEE and VCC. |
| 4 | Z | passive | Common analog output/input of the Z switch, connected to Z0 or Z1 according to input C when Enable is LOW. |
| 5 | Z0 | passive | Analog input/output Z0 of the Z switch, connected to common Z4 when selected by input C with Enable LOW; the analog signal must stay between VEE and VCC. |
| 6 | Enable | input | Active-high enable: when HIGH all analog switches are turned off; digital inputs must be held at VCC or GND levels and must be tied to a defined level, not left open (VIN 0 to 6.0 V). |
| 7 | VEE | power_in | Negative DC supply, recommended range −6.0 V to GND; sets the lower limit of the analog signal range (VIS ≥ VEE) and the device supports VEE = GND for single-supply operation. |
| 8 | GND | power_in | Ground reference for the digital control section; digital supply range is VCC − GND = 2.5 V to 6.0 V. |
| 9 | C | input | Channel-select input for the Z switch; drives the Z0/Z1 selection and must be at VCC or GND logic levels. |
| 10 | B | input | Channel-select input for the Y switch; drives the Y0/Y1 selection and must be at VCC or GND logic levels. |
| 11 | A | input | Channel-select input for the X switch; drives the X0/X1 selection and must be at VCC or GND logic levels. |
| 12 | X0 | passive | Analog input/output X0 of the X switch, connected to common X14 when selected by input A with Enable LOW; the analog signal must stay between VEE and VCC. |
| 13 | X1 | passive | Analog input/output X1 of the X switch, connected to common X14 when selected by input A with Enable LOW; the analog signal must stay between VEE and VCC. |
| 14 | X | passive | Common analog output/input of the X switch, connected to X0 or X1 according to input A when Enable is LOW. |
| 15 | Y | passive | Common analog output/input of the Y switch, connected to Y0 or Y1 according to input B when Enable is LOW. |
| 16 | VCC | power_in | Positive DC supply, recommended range 2.5 V to 6.0 V referenced to GND; the analog signal must not exceed VCC. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Negative DC supply voltage (referenced to GND), absolute maximum | VEE | -7 | 0.5 | V | Referenced to GND | 2 | |
| Positive DC supply voltage (referenced to GND), absolute maximum | VCC | -0.5 | 7 | V | Referenced to GND | 2 | |
| Positive DC supply voltage (referenced to VEE), absolute maximum | VCC | -0.5 | 7 | V | Referenced to VEE | 2 | |
| Digital input voltage (referenced to GND), absolute maximum | VIN | -0.5 | 7 | V | Referenced to GND | 2 | |
| DC current into or out of any pin | I | -20 | 20 | mA | 2 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 2 | ||
| Lead temperature | TL | 260 | °C | 1 mm from case for 10 seconds | 2 | ||
| Junction temperature under bias | TJ | 150 | °C | Under bias | 2 | ||
| Thermal resistance, junction-to-ambient, TSSOP | JA | 164 | °C/W | 2 | |||
| Power dissipation, TSSOP | PD | 450 | mW | In still air | 2 | ||
| ESD withstand voltage, Human Body Model | VESD | 2000 | V | Human Body Model (Note 1); printed as > 2000 | 2 | ||
| ESD withstand voltage, Machine Model | VESD | 200 | V | Machine Model (Note 2); printed as > 200 | 2 | ||
| ESD withstand voltage, Charged Device Model | VESD | 1000 | V | Charged Device Model (Note 3); printed as > 1000 | 2 | ||
| Latchup performance | ILATCHUP | -300 | 300 | mA | Above VCC and below GND at 125°C (Note 4) | 2 | |
| Negative DC supply voltage (referenced to GND), recommended | VEE | -6 | V | Referenced to GND | 3 | ||
| Positive DC supply voltage (referenced to GND), recommended | VCC | 2.5 | 6 | V | Referenced to GND | 3 | |
| Positive DC supply voltage (referenced to VEE), recommended | VCC | 2.5 | 6 | V | Referenced to VEE | 3 | |
| Digital input voltage, recommended | VIN | 0 | 6 | V | Referenced to GND (Note 5) | 3 | |
| Operating temperature range, all package types | TA | -55 | 125 | °C | 3 | ||
| Input rise/fall time (Channel Select or Enable inputs) | tr, tf | 0 | 100 | ns/V | VCC = 3.0 V ± 0.3 V | 3 | |
| Input rise/fall time (Channel Select or Enable inputs) | tr, tf | 0 | 20 | ns/V | VCC = 5.0 V ± 0.5 V | 3 | |
| Minimum high-level input voltage, Channel-Select or Enable inputs | VIH | 1.9 | V | VCC = 2.5 V; same limit at −55 to 125°C | 3 | ||
| Minimum high-level input voltage, Channel-Select or Enable inputs | VIH | 2.1 | V | VCC = 3.0 V; same limit at −55 to 125°C | 3 | ||
| Minimum high-level input voltage, Channel-Select or Enable inputs | VIH | 3.15 | V | VCC = 4.5 V; same limit at −55 to 125°C | 3 | ||
| Minimum high-level input voltage, Channel-Select or Enable inputs | VIH | 4.2 | V | VCC = 6.0 V; same limit at −55 to 125°C | 3 | ||
| Maximum low-level input voltage, Channel-Select or Enable inputs | VIL | 0.6 | V | VCC = 2.5 V; same limit at −55 to 125°C | 3 | ||
| Maximum low-level input voltage, Channel-Select or Enable inputs | VIL | 0.9 | V | VCC = 3.0 V; same limit at −55 to 125°C | 3 | ||
| Maximum low-level input voltage, Channel-Select or Enable inputs | VIL | 1.35 | V | VCC = 4.5 V; same limit at −55 to 125°C | 3 | ||
| Maximum low-level input voltage, Channel-Select or Enable inputs | VIL | 1.8 | V | VCC = 6.0 V; same limit at −55 to 125°C | 3 | ||
| Maximum input leakage current, Channel-Select or Enable inputs | IIN | -0.1 | 0.1 | µA | VIN = 6.0 or GND 0 V to 6.0 V; −55 to 25°C | 3 | |
| Maximum input leakage current, Channel-Select or Enable inputs | IIN | -1 | 1 | µA | VIN = 6.0 or GND 0 V to 6.0 V; 85°C | 3 | |
| Maximum quiescent supply current (per package) | ICC | 4 | µA | VCC = 6.0 V; Channel Select, Enable and VIS = VCC or GND; −55 to 25°C | 3 | ||
| Maximum quiescent supply current (per package) | ICC | 40 | µA | VCC = 6.0 V; Channel Select, Enable and VIS = VCC or GND; 85°C | 3 | ||
| Maximum quiescent supply current (per package) | ICC | 80 | µA | VCC = 6.0 V; Channel Select, Enable and VIS = VCC or GND; 125°C | 3 | ||
| Maximum ON resistance | RON | 86 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; −55 to 25°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 108 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 85°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 120 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 125°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 37 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; −55 to 25°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 46 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 85°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 55 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 125°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 26 | Ω | VCC = 3.0 V, VEE = −3.0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; −55 to 25°C (Figure 3) | 4 | ||
| Maximum ON resistance | RON | 33 | Ω | VCC = 3.0 V, VEE = −3.0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 85°C (Figure 3) | 4 | ||
| Maximum difference in ON resistance between any two channels in the same package | RON | 15 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; −55 to 25°C | 4 | ||
| Maximum difference in ON resistance between any two channels in the same package | RON | 20 | Ω | VCC = 3.0 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 85°C | 4 | ||
| Maximum difference in ON resistance between any two channels in the same package | RON | 13 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; −55 to 25°C | 4 | ||
| Maximum difference in ON resistance between any two channels in the same package | RON | 18 | Ω | VCC = 4.5 V, VEE = 0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; 85°C | 4 | ||
| Maximum difference in ON resistance between any two channels in the same package | RON | 10 | Ω | VCC = 3.0 V, VEE = −3.0 V; VIN = VIL or VIH; VIS = ½(VCC − VEE); /IS/ = 2.0 mA; −55 to 25°C | 4 | ||
| Minimum break-before-make time | tBBM | 1 | 6.5 | ns | VCC = 3.0 V, VEE = 0.0 V; VIN = VIL or VIH; VIS = VCC; RL = 300 Ω; CL = 35 pF (Figures 11 and 12) | 4 | |
| Minimum break-before-make time | tBBM | 1 | 5 | ns | VCC = 4.5 V, VEE = 0.0 V; VIN = VIL or VIH; VIS = VCC; RL = 300 Ω; CL = 35 pF (Figures 11 and 12) | 4 | |
| Minimum break-before-make time | tBBM | 1 | 3.5 | ns | VCC = 3.0 V, VEE = −3.0 V; VIN = VIL or VIH; VIS = VCC; RL = 300 Ω; CL = 35 pF (Figures 11 and 12) | 4 | |
| Maximum input capacitance, Channel-Select or Enable inputs | CIN | 10 | pF | 4 | |||
| Maximum capacitance analog I/O | CI/O | 10 | pF | All switches off; analog I/O | 4 | ||
| Maximum capacitance common O/I | CI/O | 10 | pF | All switches off; common O/I | 4 | ||
| Maximum capacitance feedthrough | CI/O | 1 | pF | All switches off; feedthrough | 4 |
CAD (KiCad official)
- Symbol:
MC74LVX4053DTR2G - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
mc74lvx4053dtr2g-etched.step/mc74lvx4053dtr2g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mc74lvx4053dtr2g.step/mc74lvx4053dtr2g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: onsemi datasheet (15 pp, sha256
f3fe07e436a3505a, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).