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RS0302YVS8

Public Made by Adom

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Jiangsu RUNIC Tech Translators, Level Shifters, VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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RS0302YVS8

Jiangsu RUNIC Tech · Translators, Level Shifters · VSSOP-8

RS0302YVS8 from Jiangsu RUNIC Tech, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference for the device.
2 VREF1 power_in Low-voltage-side reference supply for SCL1 and SDA1, which must be between 1.0 V and VREF2 - 0.6 V (datasheet lists this pin as type I).
3 SCL1 bidirectional Serial clock on the low-voltage side, an open-drain I/O rated 0 V to 5.5 V.
4 SDA1 bidirectional Serial data on the low-voltage side, an open-drain I/O rated 0 V to 5.5 V.
5 SDA2 bidirectional Serial data on the high-voltage side, an open-drain I/O rated 0 V to 5.5 V.
6 SCL2 bidirectional Serial clock on the high-voltage side, an open-drain I/O rated 0 V to 5.5 V.
7 VREF2 power_in High-voltage-side reference supply for SCL2 and SDA2, which must be between VREF1 + 0.6 V and 5.5 V (datasheet lists this pin as type I).
8 EN input Switch enable input rated 0 V to 5.5 V; when HIGH the SCL1/SDA1 and SCL2/SDA2 ports are connected, and when LOW the switch is off with high-impedance ports.

Key specifications

Parameter Value
Manufacturer Jiangsu RUNIC Tech
Package VSSOP-8
Category Logic
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC reference voltage VREF1 -0.5 7 V 7
Input voltage VI -0.5 7 V 7
Input/output voltage VI/O -0.5 7 V 7
Continuous channel current Ich 128 mA 7
Input clamp current IIK -50 mA VI<0 7
Maximum junction temperature Tj(max) 125 °C 7
Storage temperature Tstg -65 150 °C 7
Input/output voltage (SCL1, SDA1, SCL2, SDA2) VI/O 0 5.5 V SCL1, SDA1, SCL2, SDA2 7
Reference voltage (VREF1) VREF1 0 5.5 V Footnote (1): to support translation, VREF1 supports 1.0 V to VREF2 - 0.6 V 7
Reference voltage (VREF2) VREF2 0 5.5 V Footnote (1): VREF2 must be between VREF1 + 0.6 V to 5.5 V 7
Enable input voltage (EN) 0 5.5 V 7
Pass switch current IPASS 64 mA 7
Operating ambient temperature TA -40 85 °C 7
Input clamp voltage VIK -1.2 V II=-18mA, EN=0V 8
Input leakage current II 5 µA VI=5V, EN=0V 8
Input capacitance Ci(EN) 10 pF VI=3V or 0V 8
Off capacitance SCLn, SDAn Ci(off) 4 6 pF Vo=3V or 0V, EN=0V 8
On capacitance SCLn, SDAn Ci(on) 10.3 12.5 pF Vo=3V or 0V, EN=3V 8
ON-state resistance SCLn, SDAn RON 1.8 Ω VI=0V, IO=64mA, EN=4.5V 8
ON-state resistance SCLn, SDAn RON 2.3 Ω VI=0V, IO=64mA, EN=3V 8
ON-state resistance SCLn, SDAn RON 2.9 Ω VI=0V, IO=64mA, EN=2.3V 8
ON-state resistance SCLn, SDAn RON 3.9 Ω VI=0V, IO=15mA, EN=1.5V 8
ON-state resistance SCLn, SDAn RON 4 Ω VI=2.4V, IO=15mA, EN=4.5V; current sink configuration only 8
ON-state resistance SCLn, SDAn RON 56 Ω VI=2.4V, IO=15mA, EN=3V; current sink configuration only 8
ON-state resistance SCLn, SDAn RON 49 Ω VI=1.7V, IO=15mA, EN=2.3V; current sink configuration only 8
Propagation delay tPLH (SCL2/SDA2 to SCL1/SDA1), translating down tPLH 0 0.8 ns EN=3.3V, VIH=3.3V, VIL=0, VM=1.15V; CL=50pF 8
Propagation delay tPLH (SCL2/SDA2 to SCL1/SDA1), translating down tPLH 0 0.6 ns EN=3.3V, VIH=3.3V, VIL=0, VM=1.15V; CL=30pF 8
Propagation delay tPLH (SCL2/SDA2 to SCL1/SDA1), translating down tPLH 0 0.4 ns EN=3.3V, VIH=3.3V, VIL=0, VM=1.15V; CL=15pF 8
Propagation delay tPHL (SCL2/SDA2 to SCL1/SDA1), translating down tPHL 0 0.6 ns EN=3.3V, VIH=3.3V, VIL=0, VM=1.15V; CL=50pF 8
Propagation delay tPHL (SCL2/SDA2 to SCL1/SDA1), translating down tPHL 0 0.5 ns EN=3.3V, VIH=3.3V, VIL=0, VM=1.15V; CL=15pF 8
Propagation delay tPLH (SCL2/SDA2 to SCL1/SDA1), translating down tPLH 0 1 ns EN=2.5V, VIH=3.3V, VIL=0, VM=0.75V; CL=50pF 8
Propagation delay tPLH (SCL2/SDA2 to SCL1/SDA1), translating down tPLH 0 0.7 ns EN=2.5V, VIH=3.3V, VIL=0, VM=0.75V; CL=30pF 8
Propagation delay tPHL (SCL2/SDA2 to SCL1/SDA1), translating down tPHL 0 0.8 ns EN=2.5V, VIH=3.3V, VIL=0, VM=0.75V; CL=15pF 8
Propagation delay tPLH (SCL1/SDA1 to SCL2/SDA2), translating up tPLH 0 0.8 ns EN=3.3V, VIH=2.3V, VIL=0, VT=3.3V, VM=1.15V, RL=300Ω; CL=50pF 8
Propagation delay tPLH (SCL1/SDA1 to SCL2/SDA2), translating up tPLH 0 0.6 ns EN=3.3V, VIH=2.3V, VIL=0, VT=3.3V, VM=1.15V, RL=300Ω; CL=30pF 8
Propagation delay tPLH (SCL1/SDA1 to SCL2/SDA2), translating up tPLH 0 0.5 ns EN=3.3V, VIH=2.3V, VIL=0, VT=3.3V, VM=1.15V, RL=300Ω; CL=15pF 8
Propagation delay tPHL (SCL1/SDA1 to SCL2/SDA2), translating up tPHL 0 1.2 ns EN=3.3V, VIH=2.3V, VIL=0, VT=3.3V, VM=1.15V, RL=300Ω; CL=50pF 8
Propagation delay tPHL (SCL1/SDA1 to SCL2/SDA2), translating up tPHL 0 1.1 ns EN=3.3V, VIH=2.3V, VIL=0, VT=3.3V, VM=1.15V, RL=300Ω; CL=30pF 8
Propagation delay tPHL (SCL1/SDA1 to SCL2/SDA2), translating up tPHL 0 1 ns EN=3.3V, VIH=2.3V, VIL=0, VT=3.3V, VM=1.15V, RL=300Ω; CL=15pF 8
Propagation delay tPLH (SCL1/SDA1 to SCL2/SDA2), translating up tPLH 0 0.8 ns EN=2.5V, VIH=2.3V, VIL=0, VT=3.3V, VM=0.75V, RL=300Ω; CL=50pF 9
Propagation delay tPLH (SCL1/SDA1 to SCL2/SDA2), translating up tPLH 0 0.6 ns EN=2.5V, VIH=2.3V, VIL=0, VT=3.3V, VM=0.75V, RL=300Ω; CL=30pF 9
Propagation delay tPLH (SCL1/SDA1 to SCL2/SDA2), translating up tPLH 0 0.4 ns EN=2.5V, VIH=2.3V, VIL=0, VT=3.3V, VM=0.75V, RL=300Ω; CL=15pF 9
Propagation delay tPHL (SCL1/SDA1 to SCL2/SDA2), translating up tPHL 0 1.2 ns EN=2.5V, VIH=2.3V, VIL=0, VT=3.3V, VM=0.75V, RL=300Ω; CL=50pF 9
Propagation delay tPHL (SCL1/SDA1 to SCL2/SDA2), translating up tPHL 0 1 ns EN=2.5V, VIH=2.3V, VIL=0, VT=3.3V, VM=0.75V, RL=300Ω; CL=15pF 9

CAD (KiCad official)

  • Symbol: RS0302YVS8
  • Footprint: Package_SO:VSSOP-8_2.3x2mm_P0.5mm
  • 3D model: VSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: rs0302yvs8-etched.step / rs0302yvs8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); rs0302yvs8.step / rs0302yvs8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Jiangsu RUNIC Tech datasheet (16 pp, sha256 1989659b16f8a243, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF