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EFM32GG380F512G-E-QFP100

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SILICON LABS SILICON LABS, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersefm32gg380f512g-e-qfp100factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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EFM32GG380F512G-E-QFP100

SILICON LABS · SILICON LABS · LQFP-100(14x14)

EFM32GG380F512G-E-QFP100 from SILICON LABS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA0 bidirectional Port A bit 0 GPIO with alternate functions EBI_AD09, TIM0_CC0, LEU0_RX, I2C0_SDA, PRS_CH0 and GPIO_EM4WU0 (EM4 wake-up).
2 PA1 bidirectional Port A bit 1 GPIO with alternate functions EBI_AD10, TIM0_CC1, I2C0_SCL, CMU_CLK1 and PRS_CH1.
3 PA2 bidirectional Port A bit 2 GPIO with alternate functions EBI_AD11, TIM0_CC2, CMU_CLK0 and ETM_TD0.
4 PA3 bidirectional Port A bit 3 GPIO with alternate functions EBI_AD12, TIM0_CDTI0, U0_TX, LES_ALTEX2 and ETM_TD1.
5 PA4 bidirectional Port A bit 4 GPIO with alternate functions EBI_AD13, TIM0_CDTI1, U0_RX, LES_ALTEX3 and ETM_TD2.
6 PA5 bidirectional Port A bit 5 GPIO with alternate functions EBI_AD14, TIM0_CDTI2, LEU1_TX, LES_ALTEX4 and ETM_TD3.
7 PA6 bidirectional Port A bit 6 GPIO with alternate functions EBI_AD15, LEU1_RX, ETM_TCLK and GPIO_EM4WU1 (EM4 wake-up).
8 IOVDD_0 power_in Digital IO power supply 0.
9 PB0 bidirectional Port B bit 0 GPIO with alternate functions EBI_A16 and TIM1_CC0.
10 PB1 bidirectional Port B bit 1 GPIO with alternate functions EBI_A17 and TIM1_CC1.
11 PB2 bidirectional Port B bit 2 GPIO with alternate functions EBI_A18 and TIM1_CC2.
12 PB3 bidirectional Port B bit 3 GPIO with alternate functions EBI_A19, PCNT1_S0IN and US2_TX.
13 PB4 bidirectional Port B bit 4 GPIO with alternate functions EBI_A20, PCNT1_S1IN and US2_RX.
14 PB5 bidirectional Port B bit 5 GPIO with alternate functions EBI_A21 and US2_CLK.
15 PB6 bidirectional Port B bit 6 GPIO with alternate functions EBI_A22 and US2_CS.
16 VSS power_in Ground.
17 IOVDD_1 power_in Digital IO power supply 1.
18 PC0 bidirectional Port C bit 0 GPIO with analog functions ACMP0_CH0 and DAC0_OUT0ALT/OPAMP_OUT0ALT, plus EBI_A23, timer, USART, I2C0_SDA, LESENSE and PRS_CH2 alternates.
19 PC1 bidirectional Port C bit 1 GPIO with analog functions ACMP0_CH1 and DAC0_OUT0ALT/OPAMP_OUT0ALT, plus EBI_A24, timer, USART, I2C0_SCL, LESENSE and PRS_CH3 alternates.
20 PC2 bidirectional Port C bit 2 GPIO with analog functions ACMP0_CH2 and DAC0_OUT0ALT/OPAMP_OUT0ALT, plus EBI_A25, TIM0_CDTI0, US2_TX and LES_CH2.
21 PC3 bidirectional Port C bit 3 GPIO with analog functions ACMP0_CH3 and DAC0_OUT0ALT/OPAMP_OUT0ALT, plus EBI_NANDREn, TIM0_CDTI1, US2_RX and LES_CH3.
22 PC4 bidirectional Port C bit 4 GPIO with analog functions ACMP0_CH4 and DAC0_P0/OPAMP_P0, plus EBI_A26, TIM0_CDTI2, LETIM0_OUT0, PCNT1_S0IN, US2_CLK, I2C1_SDA and LES_CH4.
23 PC5 bidirectional Port C bit 5 GPIO with analog functions ACMP0_CH5 and DAC0_N0/OPAMP_N0, plus EBI_NANDWEn, LETIM0_OUT1, PCNT1_S1IN, US2_CS, I2C1_SCL and LES_CH5.
24 PB7 bidirectional Port B bit 7 GPIO with LFXTAL_P function (low-frequency crystal positive pin) and alternates TIM1_CC0, US0_TX and US1_CLK.
25 PB8 bidirectional Port B bit 8 GPIO with LFXTAL_N function (low-frequency crystal negative pin) and alternates TIM1_CC1, US0_RX and US1_CS.
26 PA7 bidirectional Port A bit 7 GPIO with alternate function EBI_CSTFT (EBI chip select output for TFT).
27 PA8 bidirectional Port A bit 8 GPIO with alternate functions EBI_DCLK (TFT dot clock) and TIM2_CC0.
28 PA9 bidirectional Port A bit 9 GPIO with alternate functions EBI_DTEN (TFT data enable) and TIM2_CC1.
29 PA10 bidirectional Port A bit 10 GPIO with alternate functions EBI_VSNC (TFT vertical sync) and TIM2_CC2.
30 PA11 bidirectional Port A bit 11 GPIO with alternate function EBI_HSNC (TFT horizontal sync).
31 IOVDD_2 power_in Digital IO power supply 2.
32 VSS power_in Ground.
33 PA12 bidirectional Port A bit 12 GPIO with alternate functions EBI_A00 and TIM2_CC0 (location 1).
34 PA13 bidirectional Port A bit 13 GPIO with alternate functions EBI_A01 and TIM2_CC1 (location 1).
35 PA14 bidirectional Port A bit 14 GPIO with alternate functions EBI_A02 and TIM2_CC2 (location 1).
36 RESETn input Reset input, active low; an external reset source must only drive this pin low during reset, letting the internal pull-up release it.
37 PB9 bidirectional Port B bit 9 GPIO with alternate functions EBI_A03 and U1_TX (location 2).
38 PB10 bidirectional Port B bit 10 GPIO with alternate functions EBI_A04 and U1_RX (location 2).
39 PB11 bidirectional Port B bit 11 GPIO with DAC0_OUT0/OPAMP_OUT0 analog output, plus TIM1_CC2, LETIM0_OUT0 and I2C1_SDA alternates.
40 PB12 bidirectional Port B bit 12 GPIO with DAC0_OUT1/OPAMP_OUT1 analog output, plus LETIM0_OUT1 and I2C1_SCL alternates.
41 AVDD_1 power_in Analog power supply 1.
42 PB13 bidirectional Port B bit 13 GPIO with HFXTAL_P function (high-frequency crystal positive pin) and alternates US0_CLK and LEU0_TX.
43 PB14 bidirectional Port B bit 14 GPIO with HFXTAL_N function (high-frequency crystal negative pin; also optional external clock input) and alternates US0_CS and LEU0_RX.
44 IOVDD_3 power_in Digital IO power supply 3.
45 AVDD_0 power_in Analog power supply 0.
46 PD0 bidirectional Port D bit 0 GPIO with ADC0_CH0, DAC0_OUT0ALT/OPAMP_OUT0ALT, OPAMP_OUT2, PCNT2_S0IN and US1_TX alternates.
47 PD1 bidirectional Port D bit 1 GPIO with ADC0_CH1, DAC0_OUT1ALT/OPAMP_OUT1ALT, TIM0_CC0, PCNT2_S1IN, US1_RX and DBG_SWO alternates.
48 PD2 bidirectional Port D bit 2 GPIO with ADC0_CH2, EBI_A27, TIM0_CC1, USB_DMPU, US1_CLK and DBG_SWO alternates.
49 PD3 bidirectional Port D bit 3 GPIO with ADC0_CH3, OPAMP_N2, TIM0_CC2, US1_CS and ETM_TD1 alternates.
50 PD4 bidirectional Port D bit 4 GPIO with ADC0_CH4, OPAMP_P2, LEU0_TX and ETM_TD2 alternates.
51 PD5 bidirectional Port D bit 5 GPIO with ADC0_CH5, OPAMP_OUT2, LEU0_RX and ETM_TD3 alternates.
52 PD6 bidirectional Port D bit 6 GPIO with ADC0_CH6, DAC0_P1/OPAMP_P1, TIM1_CC0, LETIM0_OUT0, PCNT0_S0IN, US1_RX, I2C0_SDA, LESENSE alt output 0, ACMP0_O and ETM_TD0 alternates.
53 PD7 bidirectional Port D bit 7 GPIO with ADC0_CH7, DAC0_N1/OPAMP_N1, TIM1_CC1, LETIM0_OUT1, PCNT0_S1IN, US1_TX, I2C0_SCL, CMU_CLK0, LESENSE alt output 1, ACMP1_O and ETM_TCLK alternates.
54 PD8 power_in Battery input for the Backup Power Domain (BU_VIN); CMU_CLK1 is an alternate function on location 1.
55 PC6 bidirectional Port C bit 6 GPIO with ACMP0_CH6 and alternates EBI_A05, LEU1_TX, I2C0_SDA, LESENSE channel 6 and ETM_TCLK.
56 PC7 bidirectional Port C bit 7 GPIO with ACMP0_CH7 and alternates EBI_A06, LEU1_RX, I2C0_SCL, LESENSE channel 7 and ETM_TD0.
57 VDD_DREG power_in Power supply for the on-chip voltage regulator.
58 VSS power_in Ground.
59 DECOUPLE passive Decouple output for the on-chip voltage regulator; an external capacitance of size CDECOUPLE is required at this pin.
60 PE0 bidirectional Port E bit 0 GPIO with alternates EBI_A07, TIM3_CC0, PCNT0_S0IN, U0_TX and I2C1_SDA.
61 PE1 bidirectional Port E bit 1 GPIO with alternates EBI_A08, TIM3_CC1, PCNT0_S1IN, U0_RX and I2C1_SCL.
62 PE2 bidirectional Port E bit 2 GPIO with BU_VOUT (Backup Power Domain power output) and alternates EBI_A09, TIM3_CC2, U1_TX and ACMP0_O.
63 PE3 bidirectional Port E bit 3 GPIO with BU_STAT (Backup Power Domain status) and alternates EBI_A10, U1_RX and ACMP1_O.
64 PE4 bidirectional Port E bit 4 GPIO with alternates EBI_A11 and US0_CS (location 1).
65 PE5 bidirectional Port E bit 5 GPIO with alternates EBI_A12 and US0_CLK (location 1).
66 PE6 bidirectional Port E bit 6 GPIO with alternates EBI_A13 and US0_RX (location 1).
67 PE7 bidirectional Port E bit 7 GPIO with alternates EBI_A14 and US0_TX (location 1).
68 PC8 bidirectional Port C bit 8 GPIO with ACMP1_CH0 and alternates EBI_A15, TIM2_CC0, US0_CS and LESENSE channel 8.
69 PC9 bidirectional Port C bit 9 GPIO with ACMP1_CH1 and alternates EBI_A09, TIM2_CC1, US0_CLK, LESENSE channel 9 and GPIO_EM4WU2 (EM4 wake-up).
70 PC10 bidirectional Port C bit 10 GPIO with ACMP1_CH2 and alternates EBI_A10, TIM2_CC2, US0_RX and LESENSE channel 10.
71 PC11 bidirectional Port C bit 11 GPIO with ACMP1_CH3 and alternates EBI_ALE, US0_TX and LESENSE channel 11.
72 USB_VREGI power_in USB input to the internal 3.3 V regulator.
73 USB_VREGO power_out USB decoupling for the internal 3.3 V USB regulator and regulator output.
74 PF10 bidirectional Port F bit 10 GPIO with alternates U1_TX (location 1) and USB_DM (USB D- pin).
75 PF11 bidirectional Port F bit 11 GPIO with alternates U1_RX (location 1) and USB_DP (USB D+ pin).
76 PF0 bidirectional Port F bit 0 GPIO with alternates TIM0_CC0, LETIM0_OUT0, US1_CLK, LEU0_TX, I2C0_SDA and DBG_SWCLK (debug serial-wire clock, enabled out of reset with built-in pull-down).
77 PF1 bidirectional Port F bit 1 GPIO with alternates TIM0_CC1, LETIM0_OUT1, US1_CS, LEU0_RX, I2C0_SCL, DBG_SWDIO (debug serial-wire data, built-in pull-up) and GPIO_EM4WU3.
78 PF2 bidirectional Port F bit 2 GPIO with alternates EBI_ARDY, TIM0_CC2, LEU0_TX, ACMP1_O, DBG_SWO (not enabled after reset) and GPIO_EM4WU4.
79 USB_VBUS power_in USB 5.0 V VBUS input.
80 PF12 input USB ID pin, used in OTG mode.
81 PF5 bidirectional Port F bit 5 GPIO with alternates EBI_REn, TIM0_CDTI2, USB_VBUSEN (USB 5 V VBUS enable) and PRS_CH2.
82 IOVDD_5 power_in Digital IO power supply 5.
83 VSS power_in Ground.
84 PF6 bidirectional Port F bit 6 GPIO with alternates EBI_BL0, TIM0_CC0 and U0_TX (location 0).
85 PF7 bidirectional Port F bit 7 GPIO with alternates EBI_BL1, TIM0_CC1 and U0_RX (location 0).
86 PF8 bidirectional Port F bit 8 GPIO with alternates EBI_WEn (location 1), TIM0_CC2 and ETM_TCLK (location 1).
87 PF9 bidirectional Port F bit 9 GPIO with alternates EBI_REn (location 1) and ETM_TD0 (location 1).
88 PD9 bidirectional Port D bit 9 GPIO with alternate function EBI_CS0 (EBI chip select output 0).
89 PD10 bidirectional Port D bit 10 GPIO with alternate function EBI_CS1 (EBI chip select output 1).
90 PD11 bidirectional Port D bit 11 GPIO with alternate function EBI_CS2 (EBI chip select output 2).
91 PD12 bidirectional Port D bit 12 GPIO with alternate function EBI_CS3 (EBI chip select output 3).
92 PE8 bidirectional Port E bit 8 GPIO with alternates EBI_AD00, PCNT2_S0IN (location 1) and PRS_CH3 (location 1).
93 PE9 bidirectional Port E bit 9 GPIO with alternates EBI_AD01 and PCNT2_S1IN (location 1).
94 PE10 bidirectional Port E bit 10 GPIO with alternates EBI_AD02, TIM1_CC0 (location 1), US0_TX (location 0) and BOOT_TX (bootloader TX).
95 PE11 bidirectional Port E bit 11 GPIO with alternates EBI_AD03, TIM1_CC1 (location 1), US0_RX (location 0), LESENSE alt output 5 and BOOT_RX (bootloader RX).
96 PE12 bidirectional Port E bit 12 GPIO with alternates EBI_AD04, TIM1_CC2 (location 1), US0_RX (location 3), US0_CLK (location 0), I2C0_SDA (location 6), CMU_CLK1 (location 2) and LESENSE alt output 6.
97 PE13 bidirectional Port E bit 13 GPIO with alternates EBI_AD05, US0_TX (location 3), US0_CS (location 0), I2C0_SCL (location 6), LESENSE alt output 7, ACMP0_O and GPIO_EM4WU5.
98 PE14 bidirectional Port E bit 14 GPIO with alternates EBI_AD06, TIM3_CC0 (location 0) and LEU0_TX (location 2).
99 PE15 bidirectional Port E bit 15 GPIO with alternates EBI_AD07, TIM3_CC1 (location 0) and LEU0_RX (location 2).
100 PA15 bidirectional Port A bit 15 GPIO with alternates EBI_AD08 and TIM3_CC2 (location 0).

Key specifications

Parameter Value
Manufacturer SILICON LABS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature range TSTG -40 150 °C 61
Maximum soldering temperature TS 260 °C Latest IPC/JEDEC J-STD-020 Standard 61
External main supply voltage VDDMAX 0 3.8 V 61
Voltage on any I/O pin VIOPIN -0.3 V 61
Current per I/O pin (sink) IIOMAX_SINK 100 mA 61
Current per I/O pin (source) IIOMAX_SOURCE -100 mA 61
Ambient temperature range TAMB -40 85 °C 61
Operating supply voltage VDDOP 1.98 3.8 V 61
Internal APB clock frequency fAPB 48 MHz 61
Internal AHB clock frequency fAHB 48 MHz 61
EM0 current (Running prime number calculation from flash) IEM0 219 240 µA/MHz 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current (Running prime number calculation from flash) IEM0 205 225 µA/MHz 28 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current (Running prime number calculation from flash) IEM0 206 229 µA/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current (Running prime number calculation from flash) IEM0 209 232 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current (Running prime number calculation from flash) IEM0 211 234 µA/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current (Running prime number calculation from flash) IEM0 215 242 µA/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM0 current (Running prime number calculation from flash) IEM0 243 327 µA/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 80 90 µA/MHz 48 MHz HFXO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 81 91 µA/MHz 21 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 83 99 µA/MHz 14 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 85 100 µA/MHz 11 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 90 102 µA/MHz 6.6 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM1 current IEM1 122 152 µA/MHz 1.2 MHz HFRCO, all peripheral clocks disabled, VDD= 3.0 V 62
EM2 current IEM2 1.11 1.91 µA EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=25ºC 62
EM2 current IEM2 8.81 21.51 µA EM2 current with RTC prescaled to 1 Hz, 32.768 kHz LFRCO, VDD= 3.0 V, TAMB=85ºC 62
EM3 current IEM3 0.81 1.51 µA VDD= 3.0 V, TAMB=25ºC 62
EM3 current IEM3 8.21 20.31 µA VDD= 3.0 V, TAMB=85ºC 62
EM4 current IEM4 0.02 0.08 µA VDD= 3.0 V, TAMB=25ºC 62
EM4 current IEM4 0.5 2.5 µA VDD= 3.0 V, TAMB=85ºC 62
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.96 V EM0 68
BOD threshold on falling external supply voltage VBODextthr- 1.74 1.98 V EM2 68
BOD threshold on falling internally regulated supply voltage VBODintthr- 1.57 1.7 V 68
BOD threshold on rising external supply voltage VBODextthr+ 1.85 1.98 V 68
Power-on Reset (POR) threshold on rising external supply voltage VPORthr+ 1.98 V 68
Flash erase cycles before failure ECFLASH 20000 cycles 69
Flash data retention RETFLASH 10 years TAMB<85 °C 69
Word (32-bit) programming time tW_PROG 20 µs 69
Page erase time tPERASE 20 20.4 20.8 ms LPERASE == 0 69
Page erase time tPERASE 40 40.4 40.8 ms LPERASE == 1 69
Device erase time tDERASE 161.6 ms 69
Erase current IERASE 142 mA LPERASE == 0 69
Erase current IERASE 7 mA LPERASE == 1 69
Write current IWRITE 142 mA LPERASE == 0 69
Write current IWRITE 7 mA LPERASE == 1 69
Supply voltage during flash erase and write VFLASH 1.98 3.8 V 69
Input leakage current IIOLEAK -40 0.1 40 nA High Impedance IO connected to GROUND or VDD 71
Pulse width of pulses to be removed by the glitch suppression filter tIO-GLITCH 10 50 ns 71
Supported nominal crystal frequency (HFXO) fHFXO 4 48 MHz 78
Oscillation frequency (LFRCO) fLFRCO 31.29 32.768 34.28 kHz VDD= 3.0 V, TAMB=25°C 79
Oscillation frequency, 28 MHz frequency band (HFRCO) fHFRCO 27.5 28 28.5 MHz 28 MHz frequency band; VDD= 3.0 V, TAMB=25ºC 80
Oscillation frequency (ULFRCO) fULFRCO 0.7 1.75 kHz 25°C, 3V 84
ACMP offset voltage VACMPOFFSET -12 0 12 mV BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in ACMPn_CTRL register 102
VCMP offset voltage VVCMPOFFSET -230 -40 190 mV Single-ended 104
ADC offset voltage VADCOFFSET -3 0.3 3 mV After calibration, differential 88
DAC offset voltage VDACOFFSET 2 12 mV After calibration, single-ended 97
OPAMP input offset voltage VOFFSET -13 0 11 mV Unity Gain, VSS<Vin<VDD, OPAxHCMDIS=0 98

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs exposed to light, it may be necessary to cover the top and sides with an opaque material. For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/ 422
contacts gold The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch. The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe. 413

CAD (KiCad official)

  • Symbol: EFM32GG380F512G-E-QFP100
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: efm32gg380f512g-e-qfp100-etched.step / efm32gg380f512g-e-qfp100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); efm32gg380f512g-e-qfp100.step / efm32gg380f512g-e-qfp100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SILICON LABS datasheet (433 pp, sha256 ee792fa615a39cfe, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF